UM1865 datasheet(127/132 Pages) STMICROELECTRONICS

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UM1865

SPI interface

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Figure 9. SPI wire connection

The SPI master, i.e. an application processor, always controls when to start an SPI

transaction. This can happen at any time. It is started by putting low the nCS line to activate

the BlueNRG-MS device. Then the master should provide the SPI clock. Together with the

clock, the master should output the data on the SPI bus through the MOSI line, either

dummy data or valid data. At the same time, the slave returns data from the MISO line,

because SPI is in principle a shift register.

When the SPI master wants to send data to the BlueNRG-MS, i.e. an SPI write, it sets nCS

to low, then sends the SPI clock and dummy data to read an SPI header from the BlueNRG-

MS. The SPI header format will be described in the following section. If the SPI header

indicates that the BlueNRG-MS has enough space in the buffer, the SPI master can then

send real data over the SPI bus. The SPI master should not overwrite the BlueNRG-MS SPI

buffer, otherwise the communication will fail.

When the BlueNRG-MS wants to send data to the SPI master, i.e. an SPI read, it must use

the IRQ pin, because the SPI slave cannot control the nCS line. The BlueNRG-MS will set

the IRQ pin to high, which notifies the SPI master that there is data to be read. Then the SPI

master should start an SPI transaction, reading the SPI header, and from where it will know

how many bytes it should read back from the BlueNRG-MS. The SPI master should not

read bytes other than those indicated as the SPI header, otherwise the communication will

fail.

The DataRdy (IRQ) pin of the BlueNRG-MS should work as follows: (1) it must be high when

BlueNRG-MS has data to send to the SPI master; (2) It must be high impedance when

BlueNRG-MS has no data to send to the SPI master. On the SPI master side, this pin must

be configured as an input pin. The SPI master may poll this pin, or use it as an interrupt

source, to detect when an SPI read is required. Also there should be a pull down resistor,

either on the SPI master IRQ pin or externally connected. This pull down resistor makes

sure the DataRdy value goes back to 0, so it does not confuse the SPI master to misread

data. Note that the reason that IRQ pin must be high-Z when there is no data to send is

because we also use this pin as input when BlueNRG-MS boots up. The IRQ pin value will

determine if the updater mode is required or not. After the BlueNRG-MS goes to normal

working state, the IRQ pin is configured as output for SPI interface.

Note also that the MISO also goes to high-Z when BlueNRG-MS does not send data. This

allows multi-SPI slaves on the same bus. This other SPI slave may access the bus when

BlueNRG-MS does not.

UM1865 Datasheet(PDF) 127 Page - STMicroelectronics