Low-Power, 8-Channel,

Serial 10-Bit ADC

14

______________________________________________________________________________________

PD0 CLOCK IN

SSTRB

SCLK

NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.

CS

SCLK

DIN

DOUT

CS

S

CONTROL BYTE 0

CONTROL BYTE 1

S

CONVERSION RESULT 0

B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0

CONVERSION RESULT 1

SSTRB

B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0

CONTROL BYTE 2

S

1

8

1

8

1

CS

SCLK

DIN

DOUT

S

CONTROL BYTE 0

CONTROL BYTE 1

S

CONVERSION RESULT 0

B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0

B9

B8

B7

B6

CONVERSION RESULT 1

Figure 10. Internal Clock Mode SSTRB Detailed Timing

Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing

Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing