Low-Power, 8-Channel,

Serial 10-Bit ADCs

6

________________________________________________________________________________________________

+5V

3k

DGND

DOUT

DGND

3k

DOUT

+3V

3k

DGND

DOUT

DGND

3k

DOUT

Figure 1. Load Circuits for Enable Time

Figure 2. Load Circuits for Disabled Time

Pin Description

PIN

NAME

FUNCTION

1–8

CH0–CH7

Sampling Analog Inputs

9, 13

AGND

Analog Ground. Also IN- Input for single-enabled conversions. Connect both AGND pins to

analog ground.

10

SHDN

Three-Level Shutdown Input. Pulling SHDN low shuts the MAX192 down to 10µA (max) supply cur-

rent, otherwise the MAX192 is fully operational. Pulling SHDN high puts the reference-buffer amplifi-

er in internal compensation mode. Letting SHDN float puts the reference-buffer amplifier in external

compensation mode.

11

VREF

Reference Voltage for analog-to-digital conversion. Also, Output of the Reference Buffer Amplifier.

Add a 4.7µF capacitor to ground when using external compensation mode. Also functions as an

input when used with a precision external reference.

12

REFADJ

14

DGND

Digital Ground

15

DOUT

Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when CS is

high.

16

SSTRB

Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX192 begins the A/D

conversion and goes high when the conversion is done. In external clock mode, SSTRB pulses high

for one clock period before the MSB decision. SSTRB is high impedance when CS is high

(external mode).

17

DIN

Serial Data Input. Data is clocked in at the rising edge of SCLK.

18

CS

Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT

is high impedance.

19

SCLK

Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets

the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.)

20

Positive Supply Voltage, +5V ±5%