MAX192BCAP datasheet(4/24 Pages) MAXIM

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Note 1: Tested at VDD = 5.0V; single-ended, unipolar.

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has

been calibrated.

Note 3: Grounded on-channel; sine wave applied to all off channels.

Note 4: Conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle.

Note 5: Guaranteed by design. Not subject to production testing.

Note 6: The common-mode range for the analog inputs is from AGND to VDD.

Note 7: Sample tested to 0.1% AQL.

Note 8: External load should not change during conversion for specified accuracy.

Note 9: Measured at VSUPPLY + 5% and VSUPPLY - 5% only.

Low-Power, 8-Channel,

Serial 10-Bit ADC

_______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 5V ±5%, fCLK = 2.0MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (133ksps), 4.7µF capacitor at VREF pin,

TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)

ISINK = 16mA

ISINK = 5mA

SHDN = open

SHDN = 0V

SHDN = VDD

(Note 5)

VIN = 0V or VDD

CONDITIONS

0.3

VOL

Output Voltage Low

0.4

-100

100

SHDN Max Allowed Leakage,

Mid Input

2.75

VFLT

SHDN Voltage, Floating

1.5

VDD - 1.5

VIM

SHDN Input Mid Voltage

µA

-4.0

IINL

SHDN Input Current, Low

µA

4.0

IINH

SHDN Input Current, High

0.5

VINL

SHDN Input Low Voltage

VDD - 0.5

VINH

SHDN Input High Voltage

CIN

DIN, SCLK, CS Input Capacitance

µA

±1

IIN

DIN, SCLK, CS Input Leakage

0.15

VHYST

DIN, SCLK, CS Input Hysteresis

0.8

VINL

DIN,SCLK, CS Input Low Voltage

2.4

VINH

DIN,SCLK, CS Input High Voltage

UNITS

MIN

TYP

MAX

SYMBOL

PARAMETER

Output Voltage High

VOH

ISOURCE = 1mA

Three-State Leakage Current

CS = 5V

±10

µA

Three-State Leakage Capacitance

COUT

CS = 5V (Note 5)

Positive Supply Voltage

VDD

5 ±5%

Operating mode

1.5

2.5

Fast power-down

Positive Supply Current

IDD

Full power-down

µA

Positive Supply Rejection

(Note 9)

PSR

VDD = 5V ±5%; external reference, 4.096V;

full-scale input

±0.06

±0.5

EXTERNAL REFERENCE AT REFADJ

DIGITAL INPUTS (DIN, SCLK,

–

—

–

—

–

)

DIGITAL OUTPUTS (DOUT, SSTRB)

POWER REQUIREMENTS

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