Low-Power, 8-Channel,

Serial 10-Bit ADC

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7

INPUT

SHIFT

REGISTER

CONTROL

LOGIC

INT

CLOCK

OUTPUT

SHIFT

REGISTER

+2.46V

REFERENCE

T/H

ANALOG

INPUT

MUX

SAR

ADC

IN

DOUT

SSTRB

DGND

SCLK

DIN

CH0

CH1

CH3

CH2

CH7

CH6

CH5

CH4

AGND

REFADJ

VREF

OUT

REF

CLOCK

+4.096V

20k

≈ 1.65

1

2

3

4

5

6

7

8

10

11

12

13

15

16

17

18

19

CS

SHDN

A

20

14

AGND

9

MAX192

Figure 3. Block Diagram

Detailed Description

The MAX192 uses a successive-approximation conver-

sion technique and input track/hold (T/H) circuitry to

convert an analog signal to a 10-bit digital output. A

flexible serial interface provides easy interface to

microprocessors. No external hold capacitors are

required. Figure 3 shows the block diagram for the

MAX192.

Pseudo-Differential Input

The sampling architecture of the ADC’s analog com-

parator is illustrated in the Equivalent Input Circuit

(Figure 4). In single-ended mode, IN+ is internally

switched to CH0–CH7 and IN- is switched to AGND. In

differential mode, IN+ and IN- are selected from pairs

of CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Refer

to Tables 1 and 2 to configure the channels.

In differential mode, IN- and IN+ are internally switched

to either one of the analog inputs. This configuration is

pseudo-differential to the effect that only the signal at

IN+ is sampled. The return side (IN-) must remain sta-

ble within ±0.5LSB (±0.1LSB for best results) with

respect to AGND during a conversion. Accomplish this

by connecting a 0.1µF capacitor from AIN- (the select-

ed analog input, respectively) to AGND.

During the acquisition interval, the channel selected as

acquisition interval spans three SCLK cycles and ends

on the falling SCLK edge after the last bit of the input

control word has been entered. At the end of the acqui-

sition interval, the T/H switch opens, retaining charge

The conversion interval begins with the input multiplex-

negative input (IN-). In single-ended mode, IN- is

simply AGND. This unbalances node ZERO at the input

of the comparator. The capacitive DAC adjusts during

the remainder of the conversion cycle to restore its

node ZERO to 0V within the limits of its resolution. This

action is equivalent to transferring a charge of

capacitive DAC, which in turn forms a digital represen-

tation of the analog input signal.

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

AGND

TRACK

T/H

SWITCH

10k

HOLD

CAPACITIVE DAC

VREF

ZERO

COMPARATOR

–

+

16pF

SINGLE-ENDED MODE: IN+ = CHO-CH7, IN- = AGND.

DIFFERENTIAL MODE (BIPOLAR): IN+ AND IN- SELECTED FROM PAIRS OF

CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7.

AT THE SAMPLING INSTANT,

THE MUX INPUT SWITCHES

FROM THE SELECTED IN+

CHANNEL TO THE SELECTED

IN- CHANNEL.

INPUT

MUX

Figure 4. Equivalent Input Circuit