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TLV707P Datasheet(PDF) 23 Page - Texas Instruments |
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TLV707P Datasheet(HTML) 23 Page - Texas Instruments |
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23 / 42 page ![]() COUT VOUT VIN GND PLANE CIN Represents via used for application specific connections 1 2 3 4 TLV707, TLV707P www.ti.com SBVS153D – FEBRUARY 2011 – REVISED JANUARY 2015 10 Power Supply Recommendations The device is designed to operate from an input voltage supply range between 2.0 V and 5.5 V. The input voltage range provides adequate headroom in order for the device to have a regulated output. This input supply must be well regulated (see Figure 46 through Figure 53). If the input supply is noisy, additional input capacitors with low ESR help improve the output noise performance. 11 Layout 11.1 Layout Guidelines 11.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance Place input and output capacitors as close to the device pins as possible. To improve ac performance (such as PSRR, output noise, and transient response), TI recommends that the board be designed with separate ground planes for VI and VO, with the ground plane connected only at the GND pin of the device. In addition, connect the ground connection for the output capacitor directly to the GND pin of the device. High ESR capacitors may degrade PSRR performance. 11.1.2 Package Mounting Solder pad footprint recommendations are available from TI's website at www.ti.com. The recommended land pattern for the DQN (X2SON-4) package is shown in Mechanical, Packaging, and Orderable Information. 11.2 Layout Example Figure 68. Recommended Layout Example 11.3 Thermal Considerations Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, thus protecting the regulator from damage as a result of overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, limit junction temperature to 125°C (maximum). To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection triggers at least 35°C above the maximum expected ambient condition of the particular application. This configuration produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the LDO is designed to protect against overload conditions. This circuitry is not intended to replace proper heatsinking. Continuously running the LDO into thermal shutdown degrades device reliability. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 23 |
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