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MAX7652CCB Datasheet(PDF) 15 Page - Maxim Integrated Products |
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MAX7652CCB Datasheet(HTML) 15 Page - Maxim Integrated Products |
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15 / 36 page ![]() Flash Programmable 12-Bit Integrated Data-Acquisition Systems ______________________________________________________________________________________ 15 Pin Description (continued) PIN NAME FUNCTION P3.1: Bit 1 for General Purpose I/O Port 3 25 P3.1/ TXD0 TXD0: Transmit Serial Output for Serial Port P3.0: Bit 0 for General Purpose I/O Port 3 (least significant bit) 26 P3.0/ RXD0 RXD0: Receive Serial Input for Serial Port 27 DGND Digital Ground. Connect DGND to AGND at the power source. Connect pins 27, 39, and 61 together. 28 DVDD Positive Digital Supply Voltage. Bypass with a 0.1µF in parallel with a 10µF low ESR capacitor to DGND. Connect pins 28, 40, and 62 together. P2.0: Bit 0 for General Purpose I/O Port 2 (least significant bit) 29 P2.0/A8 A8: Bit 8 for Internal Flash Memory Address P2.1: Bit 1 for General Purpose I/O Port 2 30 P2.1/A9 A9: Bit 9 for Internal Flash Memory Address P2.2: Bit 2 for General Purpose I/O Port 2 31 P2.2/A10 A10: Bit 10 for Internal Flash Memory Address P2.3: Bit 3 for General Purpose I/O Port 2 32 P2.3/A11 A11: Bit 11 for Internal Flash Memory Address P2.4: Bit 4 for General Purpose I/O Port 2 33 P2.4/A12 A12: Bit 12 for Internal Flash Memory Address P2.5: Bit 5 for General Purpose I/O Port 2 34 P2.5 Upper and Lower Internal Flash Memory Select (see Table 2) P2.6: Bit 6 for General Purpose I/O Port 2 35 P2.6 Flash Programming Mode Select (see Table 2) P2.7: Bit 7 for General Purpose I/O Port 2 (most significant bit) 36 P2.7 Flash Programming Mode Select (see Table 2) 37 PSEN Program Store Enable (active-low). Qualifies program read from external devices. To ensure flash data integrity during RST insertions, RLOAD must be greater than or equal to 200k Ω. ALE: Address Latch Enable. To ensure flash data integrity during RST insertions, RLOAD must be greater than or equal to 200k Ω. 38 ALE/ PROG PROG: Flash Memory Program Pulse 39 DGND Digital Ground. Connect pins 27, 39, and 61 together. 40 DVDD Positive Digital Supply Voltage. Bypass with a 0.1µF in parallel with a 10µF low ESR capacitor to DGND. Connect pins 28, 40 and 62 together. P0.0: Bit 0 for General Purpose I/O Port 0 (least significant bit) 41 P0.0/AD0 AD0: Bit 0 for Internal Flash Memory Data or External Memory I/O Data (least significant bit) P0.1: Bit 1 for General Purpose I/O Port 0 42 P0.1/AD1 AD1: Bit 1 for Internal Flash Memory Data or External Memory I/O Data P0.2: Bit 2 for General Purpose I/O Port 0 43 P0.2/AD2 AD2: Bit 2 for Internal Flash Memory Data or External Memory I/O Data P0.3: Bit 3 for General Purpose I/O Port 0 44 P0.3/AD3 AD3: Bit 3 for Internal Flash Memory Data or External Memory I/O Data P0.4: Bit 4 for General Purpose I/O Port 0 45 P0.4/AD4 AD4: Bit 4 for Internal Flash Memory Data or External Memory I/O Data |
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