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MAX7652CCB Datasheet(PDF) 5 Page - Maxim Integrated Products

Part # MAX7652CCB
Description  Flash Programmable 12-Bit Integrated Data-Acquisition Systems
PDF  36 Pages
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX7652CCB Datasheet(HTML) 5 Page - Maxim Integrated Products

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Flash Programmable 12-Bit Integrated
Data-Acquisition Systems
_______________________________________________________________________________________
5
TIMING CHARACTERISTICS
(MAX7651: AVDD = VPWMV = DVDD = VREF+ = +4.5 to +5.5V, VREF- = 0, fXTAL = 12MHz. MAX7652: AVDD = VPWMV = DVDD =
+2.7V to +3.6V, VREF+ = +2.5V, VREF- = 0, ACOM = AVDD/2, fXTAL = 12MHz. TA = TMIN to TMAX, unless otherwise noted. Typical
values are at TA = +25°C.) (Figure 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RST Pulse Width (High)
100 +
(64 x tCK)
µs
EXTERNAL CLOCK
Clock Frequency
fCK
12
MHz
Clock Period
tCLCL
83
ns
Clock High Time
tCHCX
25
ns
Clock Low Time
tCLCX
25
ns
Clock Rise Time
tCLCH
Guaranteed by design
10
ns
Clock Fall Time
tCHCL
Guaranteed by design
10
ns
INSTRUCTION TIMING CHARACTERISTICS
ALE Pulse Width
tLHLL
1.5tCLCL -
20
ns
Address Valid to ALE Low
tAVLL
0.5tCLCL -
15
ns
Address Hold after ALE
Low
tLLAX
0.5tCLCL -
20
ns
ALE Low to Valid
Instruction In
tLLIV
2.5tCLC
L - 35
ns
ALE Low to PSEN Low
tLLPL
0.5tCLCL
- 10
ns
PSEN Pulse Width
tPLPH
2tCLCL
- 15
ns
PSEN Low to Valid
Instruction In
tPLIV
2tCLCL -
35
ns
Input Instruction Hold
after PSEN
tPXIX
0ns
Input Instruction Float
after PSEN
tPXIZ
tCLCL -
15
ns
Address to Valid Instruction
In
tAVIV
3tCLCL -
50
ns
PSEN Low to Address Float
tPLAZ
10
ns



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