Flash Programmable 12-Bit Integrated

Data-Acquisition Systems

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25

BIT 7

(MSB)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

(LSB)

BIT 3

BIT 2

BIT 1

BIT 0

0

0

0

0

Table 11. A/D Data-0 (ADDAT0) Format—SFR Address C2H

BIT 7

(MSB)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

(LSB)

PWPS7

PWPS6

PWPS5

PWPS4

PWPS3

PWPS2

PWPS1

PWPS0

BIT 7

(MSB)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

(LSB)

PWDA7

PWDA6

PWDA5

PWDA4

PWDA3

PWDA2

PWDA1

PWDA0

Table 13. Pulse-Width Data A (PWDA) Format—SFR address DBH

BIT 7

(MSB)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

(LSB)

SIGN BIT

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

Table 10. A/D Data-1 (ADDAT1) Format—SFR Address C3H

BIT 7

(MSB)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

(LSB)

CC

CCVT

CCIE

OVRN

M3

M2

M1

M0

BIT

NAME

DESCRIPTION

7CC

Conversion Complete Flag (Read Only). The MAX7651/MAX7652 set this flag to 1 following a

conversion to indicate valid data in the ADDAT1 and ADDAT0 data SFRs (see below). The CC

bit is cleared to 0 when ADDAT1 is read by the CPU.

6

CCVT

Continuous Conversion Enable (Read/Write). When CCVT = 1, the ADC performs continuous

conversions at the rate of 224 clock cycles/conversion. Conversions continue until the MAX7651/

MAX7652 is reset or until CCVT is cleared, in which case conversions stops after the current

conversion ends.

5

CCIE

Conversion Complete Interrupt Enable (Read/Write). When CCIE = 1, interrupt 3 is generated at

the end of each conversion.

4

OVRN

Overrun Flag (Read Only). The MAX7651/MAX7652 set this flag to 1 whenever a conversion

completes while CC is set. The previous conversion result is overwritten. The OVRN bit is

cleared to 0 when ADDAT1 is read by the CPU.

3–0M3–M0

Analog Input Multiplexer Select Bits. Used to establish input configurations for single-ended or

differential conversions (see Table 6).

Table 9. A/D Control (ADCON) Format—SFR Address C5H

Note: SFRs ADDAT1 and ADDAT0 contain the results of individual A/D conversions with the formats shown in Tables 8 and 9.

A read to ADDAT1 clears the CC and OVRN flags in ADCON.

Table 12. Pulse-Width Prescaler (PWPS) Format—SFR address DAH