Flash Programmable 12-Bit Integrated

Data-Acquisition Systems

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7

TIMING CHARACTERISTICS (continued)

values are at TA = +25°C.) (Figure 3)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

-9

Data Valid to WR Transition

- 12

ns

- 20

Data Valid Before WR High

- 30

ns

- 18

Data Hold After WR High

- 18

ns

RD Low to Address Float

0ns

0

10

RD or WR High to ALE High

- 5

+11

ns

SERIAL PORT TIMING CHARACTERISTICS

SM2 = 0 (12 clocks/cycle)

Serial Port Clock Cycle

Time

SM2 = 1 (4 clocks/cycle)

ns

SM2 = 0 (12 clocks/cycle)

Output Data Setup to Clock

Rising Edge

SM2 = 1 (4 clocks/cycle)

ns

SM2 = 0 (12 clocks/cycle)

Output Data Hold after

Clock Rising Edge

SM2 = 1 (4 clocks/cycle)

ns

SM2 = 0 (12 clocks/cycle)

Input Data Hold after Clock

Rising Edge

SM2 = 1 (4 clocks/cycle)

ns

SM2 = 0 (12 clocks/cycle)

Clock Rising Edge to Input

Data Valid

SM2 = 1 (4 clocks/cycle)

ns

Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the offset and gain errors

have been nullified.

Note 3: Ground at “ON” channel; 10kHz sine-wave applied to all “off” channels.

Note 4: ALE and PSEN are in reset cycle.

Note 6: Table 1. Data Memory Stretch Values.

Note 7: The minimum frequency when writing to the internal flash is 4MHz.