MAX7652CCB datasheet(17/36 Pages) MAXIM

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Flash Programmable 12-Bit Integrated

Data-Acquisition Systems

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Detailed Description

MAX7651/MAX7652 Architecture

The MAX7651/MAX7652 are complete 12-bit data-

acquisition systems featuring an algorithmic, switched-

capacitor, analog-to-digital converter (ADC), dual

pulse-width-modulated digital-to-analog converter

(DAC), and an industry-standard 8051 microprocessor

core with a variety of I/O and timing peripherals.

Using an external oscillator with an operating frequency

between 1MHz and 12MHz, the MAX7651/MAX7652

execute the majority of its commands in only four clock

periods to yield an average speed improvement of 2.5

times over typical 8051 microprocessors requiring 12

clock periods instructions. See the MAX7651/MAX7652

Programmer’s Reference Manual for further details.

On-chip peripherals include four 8-bit parallel ports,

two serial ports, three general-purpose timers, and a

watchdog timer. The MAX7651/MAX7652 also feature

16kB in two banks of 8kB flash memory and 256 bytes

of high-speed random access memory.

Memory Organization

The MAX7651/MAX7652 support up to 64kB of external

program (read-only) memory and data (random-

access) memory in conformance with the 8051 industry

standard.

Figure 4 shows the program memory organization.

When EA is high, the CPU has access to two internal

8kB blocks of flash memory beginning at addresses

0000H (lower block) and 2000H (upper block).

Addresses 0000H–0002H and 0003H–006AH of the

lower block are reserved for the CPU reset vector and a

set of interrupt vectors, respectively (see Table 3).

Addresses 3FC0H–3FFFH of the upper block are also

reserved and cannot be accessed by the CPU.

Addresses 4000H–FFFFH are for external ROM. When

EA is low, the external ROM must be used for all pro-

gram addresses (0000H–FFFFH).

Figure 5 shows the data memory (RAM) organization.

The first 256 bytes are partitioned between two internal

128-byte blocks. The lower block (addresses 0000H–

007FH) is used for registers or scratchpad memory and

can be accessed either directly or indirectly (see the

MAX7651/MAX7652 Programmer’s Reference Manual ).

The upper block (addresses 0080H–00FFH) reflects a

set of special function registers (SFRs) when accessed

directly, and separate scratchpad memory when

accessed indirectly. Addresses 0100H–FFFFH are

reserved for external RAM.

Table 4 shows the SFR mapping to memory and Table

5 shows the SFR contents on power-up or reset.

Unshaded register designations are consistent with the

industry standard 8051. Shaded register designations

DIRECT RAM

UPPER 128

BYTES

BANK

SELECT

LOWER 128 BYTES

7FH

FFH

00H

FFH

80H

7FH

2FH

1FH

17H

0FH

07H

00H

BIT-ADDRESSABLE

REGISTERS

BANK 3

BANK 2

BANK 1

BANK 0

SFR

SPACE

DIRECT

ADDRESSING

INDIRECT

ADDRESSING

LOWER 128

BYTES

DIRECT AND

INDIRECT

ADDRESSING

EXTERNAL

INTERRUPT

VECTORS

RESET

VECTOR

FFFFH

3FFFH

3FCOH

2000H

4000H

RESERVED

1FFFH

0000H

UPPER

INTERNAL

EA = 1

3FFFH

0000H

006AH

0001H

0002H

0000H

EXTERNAL

EA = 0

LOWER

INTERNAL

EA = 1

Figure 4. Program Memory Organization

Figure 5. Data Memory (RAM) Organization

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