PCM4202 datasheet(14/30 Pages) TI

14 / 30 page

PCM4202-EP

SGLS388

– JUNE 2007

www.ti.com

ANALOG OUTPUTS

The PCM4202 includes two channels of A/D conversion, each with its own pair of differential voltage input pins.

The VINL+ (pin 4) and VINL– (pin 5) inputs correspond to Left channel input, while VINR+ (pin 25) and VINR– (pin

24) correspond to the Right channel input. The average input impedance of each input pin is 3 k

Ω.

Each analog input pair accepts a full-scale input voltage of approximately 6 VPP differential, which corresponds to

a 2.12 VRMS or 8.75 dBu input swing. The analog input should not swing below analog ground or above the VCC

power supply by more than 300 mV. Refer to the Applications Information section of this datasheet for an

example input buffer circuit.

VOLTAGE REFERENCES AND COMMON MODE BIAS VOLTAGES OUTPUTS

The PCM4202 includes two on-chip voltage references, one each for the Left and Right channels. The VREFL (pin

1) and VREFR (pin 28) outputs correspond to high reference outputs for Left and Right channels, respectively.

De-coupling capacitors are connected between each of these pins and the corresponding reference ground pin,

either AGNDL (pin 2) for the VREFL output or AGNDR (pin 27) for the VREFR output. It is recommended to have at

least a 0.1

μF X7R ceramic chip capacitor connected in parallel with a 33 μF low ESR tantalum chip capacitor for

de-coupling purposes. The VREFL and VREFR outputs should not be utilized to bias external circuitry, because

they are not buffered. Use the VCOML (pin 3) and VCOMR (pin 26) outputs to bias external circuitry, as described

in the following paragraphs.

Refer to the Applications Information section of this datasheet for the recommended voltage reference pin

connections.

The PCM4202 analog inputs are internally biased to approximately VCC/2. This bias voltage is referred to as the

common mode voltage, and is output at VCOML (pin 3) and VCOMR (pin 26), corresponding to the Left and Right

channels, respectively. These outputs provide a level shifting voltage for biasing external input buffer circuitry.

Although the VCOML and VCOMR outputs are internally buffered, the output current is limited to a few hundred μA.

It is recommended to connect these pins to external nodes with greater than 1 M

Ω impedance, or to buffer the

outputs with a voltage follower circuit when driving multiple external or low impedance nodes.

Refer to the Applications Information section of this datasheet for an example input buffer circuit that utilizes

the common-mode bias voltage outputs.

SYSTEM CLOCK INPUT

The PCM4202 requires an external system clock, from which the modulator oversampling and digital sub-system

clocks are derived. The system clock is applied at the SCKI input (pin 18). The frequency of the system clock is

dependent upon the desired PCM output sampling frequency or DSD data rate, along with the sampling mode

selection. Table 1 shows the corresponding system clock frequencies for common output sampling and data

rates, along with the corresponding sampling modes. Timing requirements for the system clock are shown in

Figure 2.

Table 1. System Clock Frequencies for Common Output Sampling and Data Rates

SAMPLING

�FREQUENCY,�f

SYSTEM CLOCK FREQUENCY (MHz)

SAMPLING

128 fS

192 fS

256 fS

384 fS

512 fS

768 fS

MODE

(kHz)

Single Rate

n/a

8.192

12.288

16.384

24.576

Single Rate

44.1

n/a

11.2896

16.9344

22.5792

33.8688

Single Rate

n/a

12.288

18.432

24.576

36.864

Dual Rate

88.2

n/a

22.5792

33.8688

n/a

Dual Rate

n/a

24.576

36.864

n/a

Quad Rate

176.4

22.5792

33.8688

n/a

Quad Rate

192

24.576

36.864

n/a

DSD Output

128 fS Data (Single Rate)

n/a

11.2896

16.9344

22.5792

33.8688

DSD Output

64 fS Data (Dual Rate)

n/a

11.2896

16.9344

n/a

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