DSDBCK

DSDL

DSD R

t

DCK HL

t

D CKP

P A R A M E T E R

D E S C R I P T IO N

M I N

M A X

U N I T S

156

70

10

ns

ns

ns

t

DCKD O

LRCK pulse width

t

DCK P

t

DCK P

t

DCK P

LRCK active edge to BCK sampling edge delay

Data setup time

PCM4202-EP

www.ti.com

SGLS388

– JUNE 2007

Figure 7. DSD Data Port Timing

HIGH-PASS FILTER

A digital high-pass filter is available for removing the DC component of the digitized input signal. The filter is

located at the output of the digital decimation filter, and is available only when using PCM output data formats.

The high-pass filter can be enabled or disabled for both the Left and Right channels using the HPFD input (pin

12). Driving the HPFD input low enables the high-pass filter. Driving the HPFD input high disables the high-pass

filter.

The

CLIPPING FLAGS

The PCM4202 includes a clipping flag output for each channel. The outputs are designated CLIPL (pin 21) and

CLIPR (pin 20), corresponding to the Left and Right channels, respectively. The clipping flags are only available

when using PCM output data formats.

A clipping flag is forced high as soon as the digital output of the decimation filter exceeds the full-scale range for

the corresponding channel. The clipping flag output is held high for a maximum of (256

N = 128 for Single Rate sampling mode, 256 for Dual Rate sampling mode, and 512 for Quad Rate sampling

mode. If the decimation filter output does not exceed the full-scale range during the initial hold period, the output

returns to a low state upon termination of the hold period.

Copyright

© 2007, Texas Instruments Incorporated

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Product Folder Link(s): PCM4202-EP