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PCM4202 Datasheet(PDF) 18 Page - Texas Instruments

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Part # PCM4202
Description  High-Performance, 24 Bit, 216 kHz Sampling, Stereo Audio Analog-to-Digital Converter
PDF  30 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

PCM4202 Datasheet(HTML) 18 Page - Texas Instruments

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LRCK
BC K
DATA
FSX
C LKR
DR
System C lock
P C M 42 0 2
D S P
SC KI
LRCK
BCK
DATA
t
BC KDO
t
BCKP
t
BCKHL
t
LRCKHL
t
LRCKH L
t
LRCKH L
P A R A M E T E R
D E S C R I P T I O N
M I N
M A X
U N I T S
5
µs
2.25
µs
78
ns
35
ns
ns
10
LRCK P e riod
LRCK High/Low Tim e
BCK P e riod
BCK High/Low Tim e
S DOUT Da ta Output De la y from BCK Fa lling Edg e
t
LRCKP
t
LRCKHL
t
BCKP
t
BCKH L
t
BCKDO
PCM4202-EP
SGLS388
– JUNE 2007
www.ti.com
In Slave mode, the BCK and LRCK signals are inputs, with the clocks being generated by a master timing
source, such as a DSP serial port, PLL clock synthesizer, or a crystal oscillator/divider circuit. The BCK rate is
typically equal to 128 fS in Single Rate sampling mode, and 64 fS in Dual or Quad Rate sampling modes.
Although other BCK clock rates are possible, they are not recommended as a result if potential clock phase
sensitivity issues, which can degrade the dynamic performance of the PCM4202. The LRCK clock must be
operated at fS, the output sampling rate.
Figure 5 illustrates the typical audio serial port connections between a PCM4202 and an audio signal processor
when using the PCM output data formats. Figure 6 illustrates the audio serial port timing for both the Master and
Slave modes of operation.
Figure 5. Typical Audio Serial Port Connections for Left Justified, Right Justified, and I2S Data Formats
Figure 6. Master and Slave Mode Audio Serial Port Timing: Left Justified, Right Justified, and Philips I2S
DSD OUTPUT MODE OPERATION
The output port DSD mode operation consists of a single DSD data clock signal, DSDBCK (pin 17), along with
two synchronous DSD data lines, DSDR (pin 15) and DSDL (pin 16). The data lines correspond to Right and Left
channels, respectively. The DSD output rate is determined by the sampling mode settings for the device,
discussed in the Sampling Modes section of this datasheet.
For DSD output data, the serial port is configured in Master mode, with the DSDBCK derived from the system
clock input, SCKI. The DSDBCK is equivalent to the oversampling clock supplied to the delta-sigma modulators.
The DSD data outputs, DSDR through DSDL, are synchronous to the DSDBCK. The clock and data lines are
then connected to a data capture or processing device.
Figure 7 illustrates the DSD port timing for both the DSD output mode.
18
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Copyright
© 2007, Texas Instruments Incorporated
Product Folder Link(s): PCM4202-EP



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