Left Channel

(a) Left Justified Data Form at

(b) Right Justified Data Form at

Right Channel

LRCKI

BCKI

DATA

M S B

LS B

L S B

M S B

LRCKI

BCKI

DATA

M S B

M S B

L S B

L S B

1/f

S

LRCKI

BCKI

DATA

M S B

LS B

M S B

L S B

D S D B C K

D SD L

D S D R

D

N -3

D

N -2

D

N -1

D

N

D

N +1

D

N +2

D

N + 3

D

N +4

PCM4202-EP

www.ti.com

SGLS388

– JUNE 2007

Figure 4. DSD Output Data Format

AUDIO SERIAL PORT OPERATION

This section provides additional details regarding the PCM4202 audio serial port, utilized for 24 bit linear PCM or

1 bit DSD output data. PCM output operation will be described in this section, while DSD output mode operation

will be described in the following section.

For PCM data formats, the serial port is comprised of three signals: BCK (pin 16), LRCK (pin 17), and DATA (pin

15). The BCK signal functions as the data (or bit) clock for the serial audio data. The LRCK is the left/right word

clock for the audio serial port. The LRCK and BCK clocks must be synchronous. The DATA signal is the serial

audio data output, with data being clocked out on the falling edge of the BCK signal. DATA carries audio data for

both the Left and Right channels.

As mentioned in the Audio Data Format section of this datasheet, the audio serial port can operate in Master or

Slave mode. In Master mode, the BCK and LRCK clock signals are outputs, derived from the system clock input,

Copyright

© 2007, Texas Instruments Incorporated

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