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AM4376 Datasheet(PDF) 243 Page - Texas Instruments |
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AM4376 Datasheet(HTML) 243 Page - Texas Instruments |
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243 / 261 page  MII_MRCLK (Input) 1 2 MII_RXD[3:0], MII_RXDV, MII_RXER (Inputs) MII_TXCLK 2 3 1 4 4 AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851B – JUNE 2014 – REVISED APRIL 2015 Table 5-120. PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK (see Figure 5-136) 10 Mbps 100 Mbps NO. UNIT MIN TYP MAX MIN TYP MAX 1 tc(TX_CLK) Cycle time, TX_CLK 399.96 400.04 39.996 40.004 ns 2 tw(TX_CLKH) Pulse Duration, TX_CLK high 140 260 14 26 ns 3 tw(TX_CLKL) Pulse Duration, TX_CLK low 140 260 14 26 ns 4 tt(TX_CLK) Transition time, TX_CLK 3 3 ns Figure 5-136. PRU-ICSS MII_TXCLK Timing Table 5-121. PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER (see Figure 5-137) 10 Mbps 100 Mbps NO. UNIT MIN TYP MAX MIN TYP MAX tsu(RXD-RX_CLK) Setup time, RXD[3:0] valid before RX_CLK 1 tsu(RX_DV-RX_CLK) Setup time, RX_DV valid before RX_CLK 8 8 ns tsu(RX_ER-RX_CLK) Setup time, RX_ER valid before RX_CLK th(RX_CLK-RXD) Hold time RXD[3:0] valid after RX_CLK 2 th(RX_CLK-RX_DV) Hold time RX_DV valid after RX_CLK 8 8 ns th(RX_CLK-RX_ER) Hold time RX_ER valid after RX_CLK Figure 5-137. PRU-ICSS MII_RXD[3:0], MII_RXDV, and MII_RXER Timing Copyright © 2014–2015, Texas Instruments Incorporated Specifications 243 Submit Documentation Feedback Product Folder Links: AM4376 AM4377 AM4378 AM4379 |
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