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AM5728 Datasheet(PDF) 236 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 236 Page - Texas Instruments |
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236 / 415 page ![]() vouti_clk vouti_vsync vouti_hsync vouti_d[23:0] vouti_de vouti_fld data_1 data_2 data_n odd even D1 D2 D3 D6 D6 D5 D6 D6 SWPS049-018 D4 AM5728, AM5726 SPRS915O – MARCH 2014 – REVISED OCTOBER 2015 www.ti.com (1) P = output vouti_clk period in ns. Figure 7-6. DPI Video Output(1)(2)(3) (1) The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock. (2) The polarity and the pulse width of vouti_hsync and vouti_vsync are programmable, refer to the DSS section of the device TRM. (3) The vouti_clk frequency can be configured, refer to the DSS section of the device TRM. NOTE To configure the desired virtual mode the user must set MODESELECT bit and DELAYMODE bitfield for each corresponding pad control register. The pad control registers are presented in Table 4-3 and described in Control Module chapter of the Device TRM. In Table 7-17 are presented the specific groupings of signals (IOSET) for use with VOUT2. Table 7-17. VOUT2 IOSETs SIGNALS IOSET1 IOSET2 BALL MUX BALL MUX vout2_d23 F2 4 AA4 6 vout2_d22 F3 4 AB3 6 vout2_d21 D1 4 AB9 6 vout2_d20 E2 4 AA3 6 vout2_d19 D2 4 D17 6 vout2_d18 F4 4 G16 6 vout2_d17 C1 4 A21 6 vout2_d16 E4 4 C18 6 vout2_d15 F5 4 A17 6 vout2_d14 E6 4 B17 6 vout2_d13 D3 4 B16 6 vout2_d12 F6 4 D15 6 236 Timing Requirements and Switching Characteristics Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM5728 AM5726 |
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