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AM5728 Datasheet(PDF) 242 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 242 Page - Texas Instruments |
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242 / 415 page  AM5728, AM5726 SPRS915O – MARCH 2014 – REVISED OCTOBER 2015 www.ti.com Table 7-21. Manual Functions Mapping for DSS VOUT2 IOSET1 (continued) BALL BALL NAME VOUT2_IOSET1_MANUAL1 CFG REGISTER MUXMODE A_DELAY (ps) G_DELAY (ps) 4 G6 vin2a_vsync0 1937 406 CFG_VIN2A_VSYNC0_OUT vout2_vsync Manual IO Timings Modes must be used to guaranteed some IO timings for VOUT2. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-22 Manual Functions Mapping for DSS VOUT2 IOSET2 for a definition of the Manual modes. Table 7-22 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers. Table 7-22. Manual Functions Mapping for DSS VOUT2 IOSET2 BALL BALL NAME VOUT2_IOSET2_MANUAL1 CFG REGISTER MUXMODE A_DELAY (ps) G_DELAY (ps) 6 E21 gpio6_14 788 0 CFG_GPIO6_14_OUT vout2_hsync F20 gpio6_15 909 26 CFG_GPIO6_15_OUT vout2_vsync F21 gpio6_16 808 0 CFG_GPIO6_16_OUT vout2_fld B14 mcasp1_aclkr 3116 360 CFG_MCASP1_ACLKR_OUT vout2_d0 G13 mcasp1_axr2 1321 1250 CFG_MCASP1_AXR2_OUT vout2_d2 J11 mcasp1_axr3 1275 1020 CFG_MCASP1_AXR3_OUT vout2_d3 E12 mcasp1_axr4 1392 1360 CFG_MCASP1_AXR4_OUT vout2_d4 F13 mcasp1_axr5 2364 240 CFG_MCASP1_AXR5_OUT vout2_d5 C12 mcasp1_axr6 1480 1090 CFG_MCASP1_AXR6_OUT vout2_d6 D12 mcasp1_axr7 1307 1180 CFG_MCASP1_AXR7_OUT vout2_d7 J14 mcasp1_fsr 1170 1000 CFG_MCASP1_FSR_OUT vout2_d1 E15 mcasp2_aclkr 2983 240 CFG_MCASP2_ACLKR_OUT vout2_d8 B15 mcasp2_axr0 1721 120 CFG_MCASP2_AXR0_OUT vout2_d10 A15 mcasp2_axr1 1067 840 CFG_MCASP2_AXR1_OUT vout2_d11 D15 mcasp2_axr4 1093 1040 CFG_MCASP2_AXR4_OUT vout2_d12 B16 mcasp2_axr5 1810 240 CFG_MCASP2_AXR5_OUT vout2_d13 B17 mcasp2_axr6 2844 240 CFG_MCASP2_AXR6_OUT vout2_d14 A17 mcasp2_axr7 1608 120 CFG_MCASP2_AXR7_OUT vout2_d15 A20 mcasp2_fsr 980 536 CFG_MCASP2_FSR_OUT vout2_d9 C18 mcasp4_aclkx 1635 1240 CFG_MCASP4_ACLKX_OUT vout2_d16 G16 mcasp4_axr0 1569 120 CFG_MCASP4_AXR0_OUT vout2_d18 D17 mcasp4_axr1 798 600 CFG_MCASP4_AXR1_OUT vout2_d19 A21 mcasp4_fsx 893 540 CFG_MCASP4_FSX_OUT vout2_d17 AA3 mcasp5_aclkx 4400 1820 CFG_MCASP5_ACLKX_OUT vout2_d20 AB3 mcasp5_axr0 4640 980 CFG_MCASP5_AXR0_OUT vout2_d22 AA4 mcasp5_axr1 4200 1120 CFG_MCASP5_AXR1_OUT vout2_d23 AB9 mcasp5_fsx 4330 1160 CFG_MCASP5_FSX_OUT vout2_d21 B26 xref_clk2 0 786 CFG_XREF_CLK2_OUT vout2_clk C23 xref_clk3 1860 760 CFG_XREF_CLK3_OUT vout2_de Manual IO Timings Modes must be used to guaranteed some IO timings for VOUT3. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-23 Manual Functions Mapping for DSS VOUT3 for a definition of the Manual modes. Table 7-23 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers. 242 Timing Requirements and Switching Characteristics Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM5728 AM5726 |
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