 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AM5728 Datasheet(PDF) 244 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
AM5728 Datasheet(HTML) 244 Page - Texas Instruments |
|
|
244 / 415 page  AM5728, AM5726 SPRS915O – MARCH 2014 – REVISED OCTOBER 2015 www.ti.com Table 7-23. Manual Functions Mapping for DSS VOUT3 (continued) BALL BALL NAME VOUT3_MANUAL1 CFG REGISTER MUXMODE A_DELAY (ps) G_DELAY (ps) 3 4 AD3 vin1a_d23 2565 0 CFG_VIN1A_D23_OUT - vout3_d0 AH6 vin1a_d3 2440 0 CFG_VIN1A_D3_OUT vout3_d4 vout3_d20 AH3 vin1a_d4 3060 0 CFG_VIN1A_D4_OUT vout3_d3 vout3_d19 AH5 vin1a_d5 2132 0 CFG_VIN1A_D5_OUT vout3_d2 vout3_d18 AG6 vin1a_d6 2313 0 CFG_VIN1A_D6_OUT vout3_d1 vout3_d17 AH4 vin1a_d7 2327 0 CFG_VIN1A_D7_OUT vout3_d0 vout3_d16 AG4 vin1a_d8 2361 0 CFG_VIN1A_D8_OUT - vout3_d15 AG2 vin1a_d9 2411 0 CFG_VIN1A_D9_OUT - vout3_d14 AD9 vin1a_de0 2529 0 CFG_VIN1A_DE0_OUT vout3_d17 vout3_de AF9 vin1a_fld0 300 327 CFG_VIN1A_FLD0_OUT - vout3_clk AE9 vin1a_hsync0 2328 0 CFG_VIN1A_HSYNC0_OUT - vout3_hsync AF8 vin1a_vsync0 2166 0 CFG_VIN1A_VSYNC0_OUT - vout3_vsync 7.8 Display Subsystem – High-Definition Multimedia Interface (HDMI) The High-Definition Multimedia Interface is provided for transmitting digital television audiovisual signals from DVD players, set-top boxes and other audiovisual sources to television sets, projectors and other video displays. The HDMI interface is aligned with the HDMI TMDS single stream standard v1.4a (720p @60Hz to 1080p @24Hz) and the HDMI v1.3 (1080p @60Hz): 3 data channels, plus 1 clock channel is supported (differential). NOTE For more information, see the High-Definition Multimedia Interface section of the device TRM. 7.9 External Memory Interface (EMIF) The device has a dedicated interface to DDR3 SDRAM. It supports JEDEC standard compliant DDR3 SDRAM devices with the following features: • 16-bit or 32-bit data path to external SDRAM memory • Memory device capacity: 128Mb, 256Mb, 512Mb, 1Gb, 2Gb, 4Gb and 8Gb devices (Single die only) • One interface with associated DDR3 PHYs NOTE For more information, see the EMIF Controller section of the Device TRM. 7.10 General-Purpose Memory Controller (GPMC) The GPMC is the unified memory controller that interfaces external memory devices such as: • Asynchronous SRAM-like memories and ASIC devices • Asynchronous page mode and synchronous burst NOR flash • NAND flash NOTE For more information, see the General-Purpose Memory Controller section of the Device TRM. 244 Timing Requirements and Switching Characteristics Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM5728 AM5726 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
