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AM5728, AM5726

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SPRS915O – MARCH 2014 – REVISED OCTOBER 2015

7.10.1 GPMC/NOR Flash Interface Synchronous Timing

CAUTION

The IO Timings provided in this section are only valid for some GPMC usage

modes when the corresponding Virtual IO Timings or Manual IO Timings are

configured as described in the tables found in this section.

Table 7-24 and Table 7-25 assume testing over the recommended operating conditions and electrical

characteristic conditions below (see Figure 7-7, Figure 7-8, Figure 7-9, Figure 7-10, Figure 7-11, and

Figure 7-12).

Table 7-24. GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - 1 Load

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

F12

tsu(dV-clkH)

Setup time, read gpmc_ad[15:0] valid before gpmc_clk high

1.9

F13

th(clkH-dV)

Hold time, read gpmc_ad[15:0] valid after gpmc_clk high

F21

tsu(waitV-clkH)

Setup time, gpmc_wait[1:0] valid before gpmc_clk high

1.9

F22

th(clkH-waitV)

Hold Time, gpmc_wait[1:0] valid after gpmc_clk high

NOTE

Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of

wait monitoring feature, see General-Purpose Memory Controller section in the Device TRM.

Table 7-25. GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - 1 Load

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

tc(clk)

Cycle time, output clock gpmc_clk period

11.3

td(clkH-nCSV)

Delay time, gpmc_clk rising edge to gpmc_cs[7:0] transition

F-0.8 (6)

F+3.17

(6)

td(clkH-nCSIV)

Delay time, gpmc_clk rising edge to gpmc_cs[7:0] invalid

E-0.8 (5)

E+3.1 (5)

td(ADDV-clk)

Delay time, gpmc_a[27:0] address bus valid to gpmc_clk first edge

B-0.8 (2)

B+3.43

(2)

td(clkH-ADDIV)

Delay time, gpmc_clk rising edge to gpmc_a[27:0] gpmc address bus invalid

-0.8

td(nBEV-clk)

Delay time, gpmc_ben[1:0] valid to gpmc_clk rising edge

B-3.8 (2)

B+2.37

(2)

td(clkH-nBEIV)

Delay time, gpmc_clk rising edge to gpmc_ben[1:0] invalid

D-0.4 (4)

D+1.1 (4)

td(clkH-nADV)

Delay time, gpmc_clk rising edge to gpmc_advn_ale transition

G-0.8 (7)

G+3.1 (7)

td(clkH-nADVIV)

Delay time, gpmc_clk rising edge to gpmc_advn_ale invalid

D-0.8 (4)

D+3.1 (4)

F10

td(clkH-nOE)

Delay time, gpmc_clk rising edge to gpmc_oen_ren transition

H-0.8 (8)

H+2.45

(8)

F11

td(clkH-nOEIV)

Delay time, gpmc_clk rising edge to gpmc_oen_ren invalid

E-0.8 (5)

E+2.1 (5)

F14

td(clkH-nWE)

Delay time, gpmc_clk rising edge to gpmc_wen transition

I-0.8 (9)

I+3.1 (9)

F15

td(clkH-Data)

Delay time, gpmc_clk rising edge to gpmc_ad[15:0] data bus transition

J-1.1 (10)

J+4.89

(10)

F17

td(clkH-nBE)

Delay time, gpmc_clk rising edge to gpmc_ben[1:0] transition

J-1.1 (10)

J+3.8 (10)

F18

tw(nCSV)

Pulse duration, gpmc_cs[7:0] low

A (1)

F19

tw(nBEV)

Pulse duration, gpmc_ben[1:0] low

C (3)

F20

tw(nADVV)

Pulse duration, gpmc_advn_ale low

K (11)

F23

td(CLK-GPIO)

Delay time, gpmc_clk transition to gpio6_16 transition

1.2

6.1

Timing Requirements and Switching Characteristics

245

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