Data Sheet

28

Rev. 1.1, 2015-07-27

TLS820F0

Block Description and Electrical Characteristics

Figure 9

Typical Watchdog Timing Diagram, Watchdog and Reset Modes

Watchdog Input “WI”

The watchdog is triggered by a falling edge at the watchdog input pin “WI”. The amplitude and slope of this signal

has to comply with the specification (Table “Watchdog Input WI” on Page 29). For details regarding test pulses,

see Figure 10 “Test Pulses Watchdog Input WI” on Page 28.

Figure 10

Test Pulses Watchdog Input WI

Trigger

WI

Ignore Time

WD Trigger

t

Current Controlled

WD-turn off

Don’t care WI

t

t

No WO assertion during

Current shut down

Normal operation

DT1

DT2

t

t

t

t

Power

Fail

Capture DT1

48ms *)

Capture DT2

Capture DT1

32ms

Capture DT1

Capture DT2

NO WD Trigger

Capture DT1

Capture DT2

96ms *)

WD Trigger

Capture DT1

Capture DT2

32ms *)

WD Trigger

32ms *)

16.5ms typ.

Capture DT1

Capture DT2

16ms *)

Normal operation

WD Trigger

Don’t care WI

ignore time

Don’t care WI

during WD-off

and ignore time

*) watchdog trigger time interrupted by correct WI signal serving the watchdog

t

t

96ms *)

Capture DT1

Capture DT2

V

WI

t

V

WI,low

V

WI,high

t

WI,ph

d

V

t

t

WI,pl