TLS820F0 datasheet(34/41 Pages) INFINEON

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Data Sheet

Rev. 1.1, 2015-07-27

TLS820F0

Block Description and Electrical Characteristics

WI ≤ VWI,dis,low), an ignore window tWI,i follows. After this, the watchdog trigger time tWI,tr starts based on the setting

of the DT pins. This behavior is defined for cases with a low current load time greater than

WO,low.

Scenario “D”

In scenario “D” the watchdog is not served within WD-trigger time

WI,tr with a trigger event at WI pin. As a result

the “WO” is set to low. This state is interrupted by setting

WI to the disable condition (VWI,dis,low ≤ VWI ≤ VWI,dis,high).

During this state, the watchdog is disabled. The watchdog output signal “WO” is kept in low state for the time of

low current load state. After leaving the disable condition (

WI ≥ VWI,dis,high or VWI ≤ VWI,dis,low), an ignore window tWI,i

follows. After this, the watchdog trigger time

WI,tr starts based on the setting of the DT pins. This behavior is defined

for cases with a low current load time less than

WO,low.

TLS820F0 Datasheet(PDF) 34 Page - Infineon Technologies AG