RF63 datasheet(16/91 Pages) ETC2

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ADVANCED COMMUNICATIONS & SENSING

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RF63

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Note for mass production: The VCO capacitance is piece to piece dependant. As such, the optimization proposed

above should be verified on several prototypes, to ensure that the population is centered on 100 mV.

3.2.6. PLL Loop Filter

To adequately reject spurious components arising from the comparison frequency Fcomp, an external 2

nd order

loop filter is employed.

RL1

LF_M

CL2

CL1

LF_P

Figure 7: Loop Filter

Following the recommendations made in section 3.2.4, the loop filter proposed in the reference design

‟s bill of

material on section 7.5.3 should be used. The loop filter settings are frequency band independent and are hence

relevant to all implementations of the RF63.

3.2.7. PLL Lock Detection Indicator

The RF63 also features a PLL lock detect indicator. This is useful for optimizing power consumption, by adjusting

the synthesizer wake up time (TS_FS), since the PLL startup time is lower than specified under nominal conditions.

The lock status can be read on bit IRQParam_PLL_lock, and must be cleared by writing a

“1” to this same register.

In addition, the lock status can be reflected in pin 23 PLL_LOCK, by setting the bit IRQParam_Enable_lock_detect.

3.2.8. Frequency Calculation

As shown in Figure 5 the PLL structure comprises three different dividers, R, P and S, which set the output

frequency through the LO. A second set of dividers is also available to allow rapid switching between a pair of

frequencies: R1/P1/S1 and R2/P2/S2. These six dividers are programmed by six bytes of the register MCParam

from addresses 6 to 11.

3.2.8.1. FSK Mode

The following formula gives the relationship between the local oscillator, and R, P and S values, when using FSK

modulation.

3.2.8.2. OOK Mode

Due to the manner in which the baseband OOK symbols are generated, the signal is always offset by the FSK

frequency deviation (Fdev - as programmed in MCParam_Freq_dev). Hence, the center of the transmitted OOK

signal is:

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