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RF63 Datasheet(PDF) 47 Page - List of Unclassifed Manufacturers |
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RF63 Datasheet(HTML) 47 Page - List of Unclassifed Manufacturers |
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47 / 91 page  ADVANCED COMMUNICATIONS & SENSING Page 47 of 91 RF63 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com 5.4.5. uC Connections RF63 IRQ_0 IRQ_1 NSS_CONFIG uC NSS_DATA SCK MOSI MISO Figure 41: uC Connections in Buffered Mode Note that depending upon the application, some uC connections may not be needed: • IRQ_0: if none of the relevant IRQ sources are used. In this case, leave floating. • IRQ_1: if none of the relevant IRQ sources are used. In this case, leave floating. • MISO: if no read register access is needed and the chip is used in Tx mode only. In this case, pull up to VDD through a 100 k Ω resistor. In addition, DATA pin (unused in buffered mode) should be pulled-up to VDD through a 100 k Ω resistor. Please refer to Table 13 for the RF63 ‟s pin configuration. 5.4.6. Buffered Mode Example • Configure all data processing related registers listed below appropriately. In this example we assume Sync word recognition is on and Fifo_fill_method=0. Tx Rx Description MCParam Data_mode_x X X Defines data operation mode (-Buffered) Fifo_size X X Defines FIFO size Fifo_thresh X X Defines FIFO threshold IRQParam Rx_stby_irq_0 X Defines IRQ_0 source in Rx & Stby modes Rx_stby_irq_1 X Defines IRQ_1 source in Rx & Stby modes Tx_irq_1 X Defines IRQ_1 source in Tx mode Fifo_fill_method X Defines FIFO filling method Fifo_fill X Controls FIFO filling status Tx_start_irq_0 X Defines Tx start condition and IRQ_0 source RXParam Sync_size X Defines Sync word size Sync_tol X Defines the error tolerance on Sync word detection SYNCParam Sync_value X Defines Sync word value Table 22: Relevant Configuration Registers in Buffered Mode (data processing related only) Tx Mode: • Program Tx start condition and IRQs: Start Tx when FIFO is not empty (Tx_start_irq_0=1) and IRQ_1 mapped to Tx_done (Tx_irq_1=1) • Go to Tx mode (and wait for Tx to be ready, see Figure 50) |
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