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ADVANCED COMMUNICATIONS & SENSING

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RF63

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5.3.3. Rx Processing

If the bit synchronizer is disabled, the raw demodulator output is made directly available on DATA pin and no DCLK

signal is provided.

Conversely, if the bit synchronizer is enabled, synchronous cleaned data and clock are made available respectively

on DATA and IRQ_1 pins. DATA is sampled on the rising edge of DCLK and updated on the falling edge as

illustrated in Figure 36.

DATA (NRZ)

DCLK

Figure 36: Rx Processing in Continuous Mode

Note that in Continuous mode it is always recommended to enable the bit synchronizer to clean the DATA signal

even if the DCLK signal is not used by the uC. (bit synchronizer is automatically enabled in Buffered and Packet

mode).

5.3.4. Interrupt Signals Mapping

The tables below give the description of the interrupts available in Continuous mode.

Rx_stby_irq_0

IRQ_0

00 (d)

Sync

RSSI

IRQ_1

DCLK

Table 17: Interrupt Mapping in Continuous Rx Mode

Note: In Continuous mode, no interrupt is available in Stby mode

IRQ_0

IRQ_1

DCLK

Table 18: Interrupt Mapping in Continuous Tx Mode

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