A13 datasheet(35/55 Pages) ETC2

35 / 55 page

Allwinner Technology CO., Ltd.

A13 Datasheet v1.30

December 10, 2012

12.

SDRAM Controller

12.1.

Overview

The SDRAM Controller (DRAMC) provides a simple, flexible, burst-optimized interface to all

industy-standard double data rate II (DDR2) ordinary SDRAM and Double data rate III (DDR3)

ordinary SDRAM. It supports up to a 512MB memory address space.

The DRAMC automatically handles memory management, initialization, and refresh operations. It

gives the host CPU a simple command interface, hiding details of the required address, page, and

burst handling procedures. All memory parameters are runtime-configurable, including timing,

memory setting, SDRAM type, and Extended-Mode-Register settings.

The DRAMC includes following features:



Support DDR2 SDRAM and DDR3 SDRAM



Support different memory device power voltage of 1.5V and 1.8V



Support DDR2/3 SDRAM of clock frequency up to DDR1066



Support memory capacity up to 512MB



15 address lines and 3 bank address lines



Data IO size can up to 16-bit for DDR2 and DDR3



Automatically generate initialization and refresh sequences



Runtime-configurable parameters setting for application flexibility



Clock frequency can be chosen for different applications



Priority of transferring through multiple ports is programmable



Support random read or write operation

12.2.

SDRAM Signal Description

Signal Name

Description

Type

DDR3_Dx

SDRAM Data Bus Bit

I/O

DDR3_DM1

SDRAM Data Mask1

A13 Datasheet(PDF) 35 Page - List of Unclassifed Manufacturers

A13 Datasheet(HTML) 35 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

Datasheet Download

Link URL