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MT8924AS Datasheet(PDF) 10 Page - Mitel Networks Corporation |
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MT8924AS Datasheet(HTML) 10 Page - Mitel Networks Corporation |
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10 / 14 page ![]() MT8924 Preliminary Information 8-12 * All AC characteristics are valid 250 µs after V DD and the clock have been applied. CL is the max. capacitive load and RL is the test pull up resistor. With Extra Bit Insert operating mode these times are 80ns longer. ** With Extra Bit Insert operating mode this time becomes 3tCK. Figure 5 - Clock Timing AC Electrical Characteristics - Clocked Timing* (T OP=0 to 70°C; VDD=5V±5%) Characteristics Sym Min Typ Max Units Test Conditions 1 Clock period tCK 230 ns 2 Clock low level width tWLCK 100 ns 3 Clock high level width tWHCK 100 ns 4 Clock rise time tRCK 25 ns 5 Clock fall time tFCK 25 ns 6 Sync. low setup time tSLSY 50 ns ** 7 Sync. low level hold time tHLSY 40 ns 8 Sync. high setup time tSHSY 80 ns 9 Sync. high width tWHSY tCK ns 10 OS propagation delay from rising edge of Clock tPDOS 100 ns CL=50pF 11 Cko propagation delay to Clock edges tPDEC 80 ns CL=50pF 12 TD setup time tSTD 80 ns 13 TD hold time tHTD 40 ns 14 TD setup time tSTF 80 ns 15 TD hold time tHTD 40 ns tHTD tWHCK tWLCK tSLSY tCK tRCK tFCK tHLSY tSHSY tPDEC tPDEC tPDOS tSTF tHTF tSTD tWHSY Cki F0i TF Cko OS TD |
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