MT9075AP datasheet(34/78 Pages) MITEL

34 / 78 page

MT9075A

Preliminary Information

4-162

Table 21 - Interrupt, Signalling and BERT

Control Word (Page 01H, Address 1AH)

(continued)

Table 21 - Interrupt, Signalling and BERT

Control Word (Page 01H, Address 1AH)

Bit

Name

Functional Description

ODE

Output Data Enable. If one, the

DSTo and CSTo output drivers

function normally. When low, DSTo

and CSTo will be tristated.

Note: When ODE =1, DSTo and

CSTo can be individually tristated

by DSToDE and CSToDE (page

01H, address 16H) respectively.

SPND

Suspend Interrupts. If one, the

IRQ output (pin 12 in PLCC, 85 in

MQFP) will be in a high-impedance

state and all interrupts will be

ignored. If zero, the IRQ output will

function normally.

INTA

Interrupt Acknowledge. A zero-to-

one or one-to-zero transition will

clear any pending interrupt and

make IRQ high.

TxCCS

Transmit

Common

Channel

Signalling. If one, the transmit

section of the device is in common

channel signalling (CCS) mode. If

zero, it is in Channel Associated

Signalling (CAS) mode.

RPSIG

Programmed

Signalling. If one, the transmit CAS

signalling

will

controlled

programming page 05H. If zero, the

transmit CAS signalling will be

controlled through the CSTi stream.

Bit

Name

Functional Description

CNTCLR

Counter Clear. If one, all status

counters are cleared and held low.

Zero for normal operation.

MSN

Most

Significant

Signalling

Nibble. If one, the CSTo and CSTi

channel

associated

signalling

nibbles will be valid in the most

significant portion of each ST-BUS

time slot. If zero, the CSTo and

CSTi channel associated signalling

nibbles will be valid in the least

significant portion of each ST-BUS

time slot.

64KCCS

Kbits/s

Common

Channel

Signalling. If one, common channel

signalling information is sourced

from CSTi, and common channel

signalling information is clocked out

of CSTo. The transmit clock is an

internal clock. This 64 KHz clock is

divided down from C4b and is

synchronous

with

the

STBUS

channel

boundaries.

The

rising

edges of the clock occur between

channels 1 and 2; 5 and 6; 9 and

10; 13 and 14; 17 and 18; 21 and

22; 25 and 26; 29 and 30. The

receive clock is synchronous with

the same channel times, but derived

from the extracted clock timebase.

The CCS receive clock is driven out

on Rx64KCK (pin 47 in PLCC, 35 in

MQFP) when this bit is set.

MT9075AP Datasheet(PDF) 34 Page - Mitel Networks Corporation

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