SN65DP149 datasheet(21/52 Pages) TI1

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IN_CLKp

IN_CLKn

IN_D[2:0]p

IN_D[2:0]n

50Q

Control Block, I2C Registers

Local I2C

Control

I2C_EN/PIN

EQ_SEL/A0

PRE_SEL

Data Registers

SWAP

PLL

PLL Control

SERDES

VBIAS

EQ_SEL

HDMI_SEL

OUT_CLKp

OUT_D[2:0]p

OUT_CLKn

OUT_D[2:0]n

EQ_CTL

SDA_CTL

SCL_CTL

VSADJ

SLEW_CTL

HDMI_SEL/A1

TERM_SEL

SLEW_SEL

PRE_SEL

Enable

TMDS

ACTIVE DDC BLOCK

HPD_SNK

HPD_SRC

190<Q

SDA_SRC

SCL_SRC

SDA_SNK

SCL_SNK

GND

VDD

VCC

1.1V

3.3V

VREG

SN65DP149, SN75DP149

www.ti.com

SLLSEL2A – SEPTEMBER 2015 – REVISED DECEMBER 2015

8 Detailed Description

8.1 Overview

The SNx5DP149 device is a Dual Mode[1] DisplayPort retiming level shifter that supports data rates up to 3.4-

Gbps for HDMI1.4b. The device takes in AC coupled HDMI/DVI signals and level shifts them to TMDS signals

while compensating for loss and jitter through its receiver equalizer and retiming functions. The SNx5DP149 in

default configuration should meet most system needs but also provides features that allow the system

implementer flexibility in design. Programming can be accomplished through I2C[4] or pin strapping.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Reset Implementation

When OE is de-asserted, control signal inputs are ignored; the Dual Mode[1] DisplayPort inputs and outputs are

high impedance. It is critical to transition the OE input from a low level to a high level after the VCC supply has

reached the minimum recommended operating voltage. Achieve this transition by a control signal to the OE

input, or by an external capacitor connected between OE and GND. To ensure that the SNx5DP149 device is

properly reset, the OE pin must be de-asserted for at least 100-

μs before being asserted. When OE is toggled in

this manner the device is reset. This requires the device to be reprogrammed if it was originally programmed

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SN65DP149 Datasheet(PDF) 21 Page - Texas Instruments

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