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SN65DP149 Datasheet(PDF) 34 Page - Texas Instruments |
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SN65DP149 Datasheet(HTML) 34 Page - Texas Instruments |
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34 / 52 page  SN65DP149, SN75DP149 SLLSEL2A – SEPTEMBER 2015 – REVISED DECEMBER 2015 www.ti.com 8.5.4.2.5 EyeScan Control Register Table 10. EyeScan Control Register ADDRESS BITS DEFAULT DESCRIPTION ACCESS PV_SYNC[3:0]. Pattern timing pulse. This field is updated for 8UI once 7:4 4’b0000 R every cycle of the PRBS generator. 1 bit per lane. PV_LD[3:0]. Load pattern-verifier controls into RX lanes. When asserted 0Eh high, the PV_TO, PV_SEL, PV_LEN, PV_CP20, and PV_CP values are 3:0 4’b0000 RWU enabled into the corresponding RX lane. These values are then latched and held when PV_LD[n] is subsequently de-asserted low. 1 bit per lane. 7:4 4’b0000 PV_FAIL[3:0]. Pattern verification mismatch detected. 1 bit per lane. RU 0Fh 3:0 4’b0000 PV_TIP[3:0]. Pattern search/training in progress. 1 bit per lane. RU PV_CP20. Customer pattern length 20 or 16 bits. 7 1’b0 0 – 16 bits RW 1 – 20 bits 6 1’b0 Reserved R PV_LEN[2:0]. PRBS pattern length 000 – PRBS7 001 – PRBS11 010 – PRBS23 5:3 3’b000 011 – PRBS31 RW 10h 100 – PRBS15 101 – PRBS15 110 – PRBS20 111 – PRBS20 PV_SEL[24:0]. Pattern select control 000 – Disabled 001 – PRBS 2:0 3’b000 RW 010 – Clock 011 – Custom 1xx – Timing only mode with sync pulse spacing defined by PV_LEN 11h 7:0 ‘h00 PV_CP[7:0]. Custom pattern data. RW 12h 7:0 ‘h00 PV_CP[15:8]. Custom pattern data. RW 7:4 4’b0000 Reserved R 13h 3:0 4’b0000 PV_CP[19:16]. Custom pattern data. Used when PV_CP20 = 1’b1. RW 7:3 5’b00000 Reserved R 14h 2:0 3’b000 PV_THR[2:0]. Pattern-verifier retain threshold. RW DESKEW_CMPLT: Indicates TMDS lane deskew has completed when 7 1'b0 R high 6:5 2’b00 Reserved R 15h 4 1’b0 BERT_CLR. Clear BERT counter (on rising edge). RSU 3 1’b0 TST_INTQ_CLR. Clear latched interrupt flag. RSU 2:0 3’b000 TST_SEL[2:0]. Test interrupt source select. RW PV_DP_EN[3:0]. Enabled datapath verified based on DP_TST_SEL, 1 bit 7:4 4’b0000 RW per lane. 3 1’b0 Reserved R DP_TST_SEL[2:0] Selects pattern reported by BERT_CNT[11:0], TST_INT[0] and TST_INTQ[0]. PV_DP_EN is non-zero 000 – TMDS disparity or data errors 16h 001 – FIFO errors 010 – FIFO overflow errors 2:0 3'b000 RW 011 – FIFO underflow errors 100 – TMDS deskew status 101 – Reserved 110 – Reserved 111 – Reserved 7:4 4’b0000 TST_INTQ[3:0]. Latched interrupt flag. 1 bit per lane RU 17h 3:0 4’b0000 TST_INT[3:0]. Test interrupt flag. 1 bit per lane. RU 18h 7:0 ‘h00 BERT_CNT[7:0]. BERT error count. Lane 0 RU 34 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: SN65DP149 SN75DP149 |
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