ACE25C200G datasheet(22/48 Pages) ACE

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ACE25C200G

2M BIT SPI NOR FLASH

VER 1.1

Quad Output Fast Read (6BH)

See Figure 10, the Quad Output Fast Read instruction is followed by 3-byte address (A23-A0) and

a dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents

are shifted out 4-bit per clock cycle from IO3, IO2, IO1 and IO0. The first byte addressed can be at

any location. The address is automatically incremented to the next higher address after each byte of

data is shifted out.

Figure 10 Quad Output Fast Read Sequence Diagram

Figure 10

Dual I/O Fast Read (BBH)

See Figure 11, the

Dual I/O Fast Read instruction is similar to the Dual Output Fast Read

instruction but with the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode”

byte 2-bit per clock by SI and SO, each bit being latched in during the rising edge of SCLK, then the

memory contents are shifted out 2-bit per clock cycle from SI and SO. The first byte addressed can be

at any location. The address is automatically incremented to the next higher address after each byte

of data is shifted out.

Figure 11 Dual I/O Fast Read Sequence Diagram (Initial command or previous M5-4≠10)

Figure 11

ACE25C200G Datasheet(PDF) 22 Page - ACE Technology Co., LTD.