ACE25C200G datasheet(37/48 Pages) ACE

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ACE25C200G

2M BIT SPI NOR FLASH

VER 1.1

Chip Erase (60/C7H)

The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A

Write Enable instruction must be executed before the device will accept the Chip Erase Instruction

(Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and

shifting the instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in Figure

29.

The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip

Erase instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction

will commence for a time duration of tCE. While the Chip Erase cycle is in progress,

Chip Erase cycle is in

progress, the Read Status Register instruction may still be accessed to check the status of the WIP bit.

The WIP bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is

ready to accept other Instructions again. After the Chip Erase cycle has finished the Write Enable

Latch (WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will not be executed

if any page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Table 6 &

7) is not executed.

Figure 29 Chip Erase Sequence Diagram

Figure 29

Erase / Program Suspend (75H)

The Erase/Program Suspend instruction allows the system to interrupt a Sector or Block Erase

operation, then read from or program data to any other sector. The Erase/Program Suspend

instruction also allows the system to interrupt a Page Program operation and then read from any other

page or erase any other sector or block. The Erase/Program Suspend instruction sequence

is shown in Figure 30.

The Write Status Registers instruction (01h) and Erase instructions (20h, D8h, C7h, 60h, 44h) are

not allowed during Erase Suspend. Erase Suspend is valid only during the Sector or Block erase operation. If

written during the Chip Erase operation, the Erase Suspend instruction is ignored. The Write Status Registers

instruction (01h), and Program instructions (02h, 42h) are not allowed during Program Suspend. Program

Suspend is valid only during the Page Program operation.

Figure 30 Erase/Program Suspend Command Sequence

Figure 30

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