ACE25C200G datasheet(24/48 Pages) ACE

24 / 48 page

ACE25C200G

2M BIT SPI NOR FLASH

VER 1.1

Quad I/O Fast Read with “Continuous Read Mode”

See Figure 14, the Fast Read Quad I/O command can further reduce instruction overhead through

setting the “Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), The upper nibble

of the (M7-4) controls the length of the next Fast Read Quad I/O command through the inclusion or

exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”).

However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If

the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O command (after /CS

is raised and then lowered) does not require the EBH instruction code, This reduces the command

sequence by eight clocks and allows the Read address to be immediately entered after /CS is

asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next command (after

/CS is raised and then lowered) requires the first byte instruction code, thus returning to normal

operation. A “Continuous Read Mode” Reset command can also be used to reset (M7-0) before

issuing normal commands (see Continuous Read Mode Reset (FFH or FFFFH)).

Figure 14 Quad I/O Fast Read Sequence Diagram (Previous command set M5-4 =10)

Figure 14

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