ACE25C200G datasheet(43/48 Pages) ACE

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ACE25C200G

2M BIT SPI NOR FLASH

VER 1.1

AC Electrical Characteristics

Table19

Symbol

Parameter

Min.

Typ.

Max.

Unit.

Clock

frequency

for

all

instructions,

except

Read

Data(03H)

DC.

108

MHz

Clock freq. Read Data instruction(03H)

DC.

MHz

tCLH

Serial Clock High Time

tCLL

Serial Clock Low Time

tCLCH

Serial Clock Rise Time (Slew Rate)

0.1

(1)

V/ns

tCHCL

Serial Clock Fall Time (Slew Rate)

0.1

(1)

V/ns

tSLCH

/CS Active Setup Time

tCHSH

/CS Active Hold Time

tSHCH

/CS Not Active Setup

Time

tCHSL

/CS Not Active Hold Time

tSHSL

/CS High Time（read/write）

tSHQZ

Output

Disable Time

tCLQX

Output

Hold Time

tDVCH

Data In Setup Time

tCHDX

Data In Hold Time

tHLCH

/Hold Low Setup Time (relative to Clock)

tHHCH

/Hold High Setup Time (relative to Clock)

tCHHL

/Hold High Hold Time (relative to Clock)

tCHHH

/Hold Low Hold Time (relative to Clock)

tHLQZ

/Hold Low To High-Z Output

tHHQX

/Hold Low To Low-Z Output

tCLQV

Clock Low To Output Valid

tWHSL

Write Protect Setup Time Before /CS Low

tSHWL

Write Protect Hold Time After /CS High

100

tDP

/CS High To Deep Power-Down Mode

0.1

µs

tRES1

/CS High To Standby Mode Without Electronic Signature

Read

µs

tRES2

/CS High To Standby Mode With Electronic Signature Read

1.5

µs

tSUS

/CS High To Next Instruction After Suspend

µs

Write Status Register Cycle Time

(2)

tBP1

Byte Program Time (First Byte) (3)

µs

tBP2

Additional Byte Program Time (After First Byte) (3)

2.8

µs

tPP

Page Programming Time

0.7

2.4

tSE

Sector Erase Time

300

tBE

Block Erase Time(32K Bytes/64K Bytes)

0.3/0.5

0.75/1.5

tCE

Chip Erase Time

Note:

1. Tested with clock frequency lower than 50 MHz.

2. tW can be up to 45 ms at -40℃ during the characterization of the current design. It will be improved in the future design.

3. For multiple bytes after first byte within a page, tBPn = tBP1 + tBP2 * N, where N is the number of bytes programmed

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