ADM1260 datasheet(39/71 Pages) AD

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Data Sheet

ADM1260

Rev. 0 | Page 39 of 71

CONFIGURATION REGISTERS

UPDATING THE MEMORY, ENABLING BLOCK

ERASURE, AND DOWNLOADING EEPROM

The ADM1260 contains both volatile and nonvolatile memory,

which must be set up correctly if any alterations to the config-

uration are to be updated properly in the device. The volatile

memory of the device is constructed with double buffered latches.

The register and bit details in Figure 51 show the configurations

required to perform the following actions:



Update the volatile memory in real time.



Update the volatile memory offline, then update the

memory all at once.



Enable block erasure.



Download EEPROM contents to the RAM.

There are also a number of configuration bits that update the

sequencing engine. These bits are detailed in Table 13.

POWER-UP

(VCC > 2.5V)

EEPROM

SMBus

DEVICE

CONTROLLER

LATCH A

LATCH B

FUNCTION,

FOR EXAMPLE,

OV THRESHOLD

ON VP1

Figure 51. Configuration Update Flow Diagram

Table 13. Configuration Bits to Update the Sequencing Engine

Address

Bits

Bit Names

R/W

Description

0x90

UPDCFG

[7:3]

Not applicable

These bits cannot be used.

EEBLKERS

R/W

This bit enables the configuration EEPROM block erasure.

CFGUPD

This bit updates the configuration registers from holding

other registers; this bit self clears.

CONTUPD

R/W

This bit enable the continuous update of the configuration

registers.

0xD8

UDOWNLD

[7:1]

Not applicable

These bits cannot be used.

EEDWNLD

This bit downloads configuration data from EEPROM (which

also happens automatically at power-up); this bit self clears on

completion.

0xF4

MANID

[7:0]

MANID

These bits are the manufacturer ID; they return 0x41 and can

be used to verify communication with the device.

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