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ADM1260 Datasheet(PDF) 49 Page - Analog Devices |
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ADM1260 Datasheet(HTML) 49 Page - Analog Devices |
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49 / 71 page  Data Sheet ADM1260 Rev. 0 | Page 49 of 71 Table 15. Registers Used to Configure the Outputs1 Output Reg. Addr. Register Name Bits Bit Name R/W Description PDO1 0x07 PDO1CFG 7 Not applicable This bit cannot be used. [6:4] CFG6 to CFG4 R/W These bits control the logic source driving the PDOx pin, that is, the SE, the internal clock, or the SMBus, directly. CFG6 CFG5 CFG4 PDOx Status 0 0 0 Disabled, with a weak pull-down resistor 0 0 1 Enabled; follows the logic driven by the SE 0 1 0 Enables SMBus data, driven low 0 1 1 Enables SMBus data, driven high 1 X X Enables the 100 kHz clock out onto the pin [3:0] CFG3 to CFG0 R/W These bits determine the format of the pull-up resistor on the PDOx pin. CFG3 CFG2 CFG1 CFG0 PDOx Pull-Up Resistor 0 0 0 X None 0 0 1 X Pull-up to 12 V charge pump voltage 0 1 0 0 Weak, open-drain pull-up to VP1 0 1 0 1 Push-pull pull-up to VP1 0 1 1 0 Weak, open-drain pull-up to VP2 0 1 1 1 Push-pull pull-up to VP2 1 0 0 0 Weak, open-drain pull-up to VP3 1 0 0 1 Push-pull pull-up to VP3 1 0 1 0 Weak, open-drain pull-up to VP4 1 0 1 1 Push-pull pull-up to VP4 1 1 1 0 Weak, open-drain pull-up to VDDCAP 1 1 1 1 Push-pull pull-up to VDDCAP PDO2 0x0F PDO2CFG 7 Not applicable This bit cannot be used. [6:4] CFG6 to CFG4 R/W These bits control the logic source driving the PDOx pin, that is, the SE, the internal clock, or the SMBus, directly. CFG6 CFG5 CFG4 PDOx Status 0 0 0 Disabled, with a weak pull-down resistor 0 0 1 Enabled; follows the logic driven by the SE 0 1 0 Enables SMBus data, driven low 0 1 1 Enables SMBus data, driven high 1 X X Enables the 100 kHz clock out onto the pin [3:0] CFG3 to CFG0 R/W These bits determine the format of the pull-up resistor on the PDOx pin. CFG3 CFG2 CFG1 CFG0 PDOx Pull-Up Resistor 0 0 0 X None 0 0 1 X Pull-up to 12 V charge pump voltage 0 1 0 0 Weak, open-drain pull-up to VP1 0 1 0 1 Push-pull pull-up to VP1 0 1 1 0 Weak, open-drain pull-up to VP2 0 1 1 1 Push-pull pull-up to VP2 1 0 0 0 Weak, open-drain pull-up to VP3 1 0 0 1 Push-pull pull-up to VP3 1 0 1 0 Weak, open-drain pull-up to VP4 1 0 1 1 Push-pull pull-up to VP4 1 1 1 0 Weak, open-drain pull-up to VDDCAP 1 1 1 1 Push-pull pull-up to VDDCAP |
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