ADM1260 datasheet(33/71 Pages) AD

33 / 71 page

Data Sheet

ADM1260

Rev. 0 | Page 33 of 71

START BY

MASTER

ACK BY

SLAVE

ACK BY

SLAVE

ACK BY

SLAVE

ACK BY

SLAVE

FRAME 2

COMMAND CODE

FRAME 1

SLAVE ADDRESS

FRAME N

DATA BYTE

FRAME 3

DATA BYTE

SCL

SDA

R/W

STOP

MASTER

SCL

(CONTINUED)

SDA

(CONTINUED)

Figure 38. General SMBus Write Timing Diagram

START BY

MASTER

ACK BY

SLAVE

ACK BY

MASTER

ACK BY

MASTER

NACK

FRAME 2

DATA BYTE

FRAME 1

SLAVE ADDRESS

FRAME N

DATA BYTE

FRAME 3

DATA BYTE

SCL

SDA

R/W

STOP

MASTER

SCL

(CONTINUED)

SDA

(CONTINUED)

Figure 39. General SMBus Read Timing Diagram

SCL

SDA

tSU;STO

tHD;STA

tSU;STA

tSU;DAT

tHD;DAT

tHD;STA

tHIGH

tBUF

tLOW

Figure 40. Serial Bus Timing Diagram

SMBus PROTOCOLS FOR RAM AND EEPROM

The ADM1260 contains volatile registers (RAM) and nonvolatile

registers (EEPROM). User RAM occupies Address 0x00 to

Address 0xDF, and the EEPROM occupies Address 0xF800 to

Address 0xFBFF.

Data can be written to and read from both the RAM and the

EEPROM as single data bytes. Data can be written only to

unprogrammed EEPROM locations. To write new data to a

programmed location, the location contents must first be erased.

EEPROM erasure cannot be done at the byte level. The EEPROM

is arranged as 32 pages of 32 bytes each, and an entire page

must be erased.

Page erasure is enabled by setting Bit 2 in the UPDCFG register

(Address 0x90) to 1. If this bit is not set, page erasure cannot

occur, even if the command byte (0xFE) is programmed across

the SMBus.

ADM1260 Datasheet(PDF) 33 Page - Analog Devices

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