AD7761 datasheet(49/69 Pages) AD

49 / 69 page

Data Sheet

AD7761

Rev. 0 | Page 49 of 69

To receive data, the master must pulse the SYNC_IN pin to

reset the filter and force DRDY low. DRDY subsequently goes

high to indicate to the master device that the device has valid

settled data available. Unlike standard mode, DRDY remains

high for the number of clock periods of valid data before it goes

low again; thus, in this conversion mode, it is an active high

frame of the data.

When the master pulses SYNC_IN and the AD7761 receives the

rising edge of this signal, the digital filter is reset and the full

settling time of the filter elapses before the data is available. The

duration of the settling time depends on the filter path and

decimation rate. Running one-shot mode with the sinc5 filter

allows the fastest throughput, because this filter has a lower

settling time than the wideband filter.

As soon as settled data is available on any channel, the device

outputs data from all channels. The contents of Bit 6 of the channel

header status bits indicates whether the data is fully settled.

The period before the data is settled on all channels (tSETTLE) is

shown in Figure 74. After the data has settled on all channels,

DRDY is asserted high and the device outputs the required settled

data on all channels before DRDY is asserted low. If the user config-

ures the same filter and decimation rate on each ADC, the data is

settled for all channels on the first DRDY output frame, which

avoids a period of unsettled data prior to the settled data and

ensures that all data is output at the same time on all ADCs. The

device then waits for another SYNC_IN signal before outputting

more data.

Because all the ADCs are sampling continuously, one-shot

mode affects the sampling theory of the AD7761. Particularly, a

user periodically sending a SYNC_IN pulse to the device is a

form of subsampling of the ADC output. The subsampling occurs

at the rate of the SYNC_IN pulses. The SYNC_IN pulse must be

synchronous with the master clock to ensure coherent sampling

and to reduce the effects of jitter on the frequency response.

Daisy-Chaining

Daisy-chaining devices allows numerous devices to use the

same data interface lines by cascading the outputs of multiple

ADCs from separate AD7761 devices. Only one ADC device

has its data interface in direct connection with the digital host.

For the AD7761, this connection can be implemented by

cascading DOUT0 and DOUT1 through a number of devices, or

using only DOUT0; whether two data output pins or only one

data output pin is enabled depends on the FORMATx pins. The

ability to daisy-chain devices and the limit on the number of

devices that can be handled by the chain is dependent on the

power mode, DCLK, and the decimation rate employed.

The maximum usable DCLK frequency allowed when daisy-

chaining devices is limited by the combination of timing

specifications in Table 2 or Table 4, as well as by the propagation

delay of the data between devices and any skew between the MCLK

signals at each AD7761 device. The propagation delay and MCLK

skew are dependent on the PCB layout and trace lengths.

This feature is especially useful for reducing component count

and wiring connections, for example, in isolated multiconverter

applications or for systems with a limited interfacing capacity.

When daisy-chaining on the AD7761, DOUT6 and DOUT7

become serial data inputs, and DOUT0 and DOUT1 remain as

serial data outputs under the control of the FORMATx pins.

START

SYNC_IN

DOUT1

DOUT0

DRDY

DOUT6

MCLK

DOUT7

SYNC_OUT

DSP/

FPGA

START

SYNC_IN

DOUT1

DOUT0

DRDY

DOUT6

MCLK

DOUT7

SYNC_OUT

DNC

IOVDD

START

SYNC_IN

DOUT1

DOUT0

DRDY

DOUT6

MCLK

DOUT7

SYNC_OUT

DNC

AD7761

SYNCHRONIZATION

LOGIC

DIGITAL FILTER

SYNCHRONIZATION

LOGIC

DIGITAL FILTER

SYNCHRONIZATION

LOGIC

DIGITAL FILTER

MASTER

CLOCK

Figure 75. Daisy-Chaining Multiple AD7761 Devices

Figure 75 shows an example of daisy-chaining AD7761 devices,

when FORMATx = 01. In this case, the DOUT1 and DOUT0

pins of the AD7761 devices are cascaded to the DOUT6 and

DOUT7 pins of the next device in the chain. Data readback is

analogous to clocking a shift register where data is clocked out on

the rising edge of DCLK. Input data on the DOUT6 and DOUT7

pins is sampled on the falling edge of DCLK.

The scheme operates by passing the output data of the DOUT0

and DOUT1 pins of an AD7761 upstream device to the DOUT6

and DOUT7 inputs of the next AD7761 device downstream in the

chain. The data then continues through the chain until it is

clocked onto the DOUT0 and DOUT1 pins of the final down-

stream device in the chain.

Daisy-chaining can be achieved in a similar manner on the

AD7761 when using only the DOUT0 pin. In this case, only

Pin 21 of the AD7761 is used as the serial data input pin.

In a daisy-chained system of AD7761 devices, two successive

synchronization pulses must be applied to guarantee that all ADCs

are synchronized. Two synchronization pulses are also required in a

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