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AD7761 Datasheet(PDF) 66 Page - Analog Devices |
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AD7761 Datasheet(HTML) 66 Page - Analog Devices |
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66 / 69 page  AD7761 Data Sheet Rev. 0 | Page 66 of 69 Table 52. Per Channel 24-Bit Offset Registers, Three 8-Bit Registers for Each Channel, Split Up as MSB, MID, and LSB Address Name Description Reset Access MSB Mid LSB MSB Mid LSB 0x1E 0x1F 0x20 Channel 0 offset Channel 0 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 RW 0x21 0x22 0x23 Channel 1 offset Channel 1 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 RW 0x24 0x25 0x26 Channel 2 offset Channel 2 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 RW 0x27 0x28 0x29 Channel 3 offset Channel 3 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 RW 0x2A 0x2B 0x2C Channel 4 offset Channel 4 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 RW 0x2D 0x2E 0x2F Channel 5 offset Channel 5 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 RW 0x30 0x31 0x32 Channel 6 offset Channel 6 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 RW 0x33 0x34 0x35 Channel 7 offset Channel 7 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 RW GAIN REGISTERS Each ADC channel has an associated gain coefficient. The coefficient is stored in three single-byte registers split up as MSB, MID, and LSB. Each of the gain registers are factory programmed. Nominally, this gain is around the value 0x555555 (for an ADC channel). The user can overwrite the gain register setting; however, after a reset or power cycle, the gain register values revert to the hard coded programmed factory setting. Table 53. Per Channel 24-Bit Gain Registers, Three 8-Bit Registers for Each Channel, Split Up as MSB, MID, and LSB Address Name Description Reset Access MSB Mid LSB MSB Mid LSB 0x36 0x37 0x38 Channel 0 gain Channel 0 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW 0x39 0x3A 0x3B Channel 1 gain Channel 1 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW 0x3C 0x3D 0x3E Channel 2 gain Channel 2 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW 0x3F 0x40 0x41 Channel 3 gain Channel 3 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW 0x42 0x43 0x44 Channel 4 gain Channel 4 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW 0x45 0x46 0x47 Channel 5 gain Channel 5 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW 0x48 0x49 0x4A Channel 6 gain Channel 6 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW 0x4B 0x4C 0x4D Channel 7 gain Channel 7 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW SYNC PHASE OFFSET REGISTERS The AD7761 has one synchronization signal for all channels. The sync phase offset register allows the user to vary the phase delay on each of the channels relative to the synchronization edge received on the SYNC_IN pin. See the Sync Phase Offset Adjustment section for details on the use of this function. Table 54. Per Channel 8-Bit Sync Phase Offset Registers Address Name Description Reset Access 0x4E Channel 0 sync offset Channel 0 sync phase offset register 0x00 RW 0x4F Channel 1 sync offset Channel 1 sync phase offset register 0x00 RW 0x50 Channel 2 sync offset Channel 2 sync phase offset register 0x00 RW 0x51 Channel 3 sync offset Channel 3 sync phase offset register 0x00 RW 0x52 Channel 4 sync offset Channel 4 sync phase offset register 0x00 RW 0x53 Channel 5 sync offset Channel 5 sync phase offset register 0x00 RW 0x54 Channel 6 sync offset Channel 6 sync phase offset register 0x00 RW 0x55 Channel 7 sync offset Channel 7 sync phase offset register 0x00 RW ADC DIAGNOSTIC RECEIVE SELECT REGISTER Address: 0x56, Reset: 0x00, Name: Diagnostic Rx The AD7761 ADC diagnostic allows the user to select a zero-scale, positive full-scale, or negative full-scale input to the ADC, which can be converted to verify the correct operation of the ADC channel. This register enables the diagnostic. Enable the receive (Rx) for each channel and set each bit in this register to 1. The ADC diagnostic feature depends on some features of the analog input precharge buffers. The user must ensure that the analog input precharge buffers are enabled on the channels that are selected to receive the diagnostic voltages internally. |
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