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FT810Q Datasheet(PDF) 37 Page - Future Technology Devices International Ltd.

Part # FT810Q
Description  Embedded Video Engine
PDF  60 Pages
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Manufacturer  FTDI [Future Technology Devices International Ltd.]
Direct Link  http://www.ftdichip.com
Logo FTDI - Future Technology Devices International Ltd.

FT810Q Datasheet(HTML) 37 Page - Future Technology Devices International Ltd.

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Copyright © 2015 Future Technology Devices International Limited
37
Document No.: FT_001165
FT81X
Embedded Video Engine
Datasheet Version 1.2
Clearance No.:
FTDI#440
4.8.3 Power Modes
When the supply to VCCIO and VCC is applied, the internal regulator is powered by VCC. An internal POR
pulse will be generated during the regulator power up until it is stable. After the initial power up, the
FT81x will stay in the SLEEP state. When needed, the host can set the FT81x to the ACTIVE state by
performing a SPI ACTIVE command. The graphics engine, the audio engine and the touch engine are only
functional in the ACTIVE state. To save power the host can send a command to put the FT81x into any of
the low power modes: STANDBY, SLEEP and POWERDOWN. In addition, the host is allowed to put the
FT81x in POWERDOWN mode by driving the PD_N pin to low, regardless of what state it is currently in.
Refer to
Figure 4-11 for the power state transitions.
Figure 4-11 Power State Transition
4.8.3.1 ACTIVE state
In ACTIVE state, the FT81x is in normal operation. The clock oscillator and PLL are functioning. The
system clock applied to the FT81x core engines is enabled.
4.8.3.2 STANDBY state
In STANDBY state, the clock oscillator and PLL remain functioning; the system clock applied to the FT81x
core engines is disabled. All register contents are retained.
4.8.3.3 SLEEP state
In SLEEP state, the clock oscillator, PLL and system clock applied to the FT81x core engines are disabled.
All register contents are retained.
4.8.3.4 POWERDOWN state
In POWERDOWN state, the clock oscillator, the PLL and the system clock applied to the FT81x core is
disabled. The core engines are powered down while the SPI interface for host commands remains
functional. All register contents are lost and reset to default when the chip is next switched on. The
internal regulator remains on.
POWERDOWN
SLEEP
STANDBY
VCC/VCCIO
Power ON
Toggle PD_N from high
to low
ACTIVE
Toggle PD_N from low
to high
Toggle PD_N from high
to low
Toggle PD_N from high to low or
Write command “POWERDOWN”
Write command “STANDBY”
Write command
“SLEEP”
Write command
“ACTIVE”
Write command
“ACTIVE”



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