DP83843 datasheet(39/87 Pages) NSC

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6.0 DP83843 Application (Continued)

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system design, empirical data has shown a resultant

improvement (reduction) in radiated emissions testing.

Additionally, by eliminating power plane partitioning within

the system VCC and system ground domains, speciﬁc

impedance controlled signal routing can remain uninter-

rupted.

Figure 24 illustrates a way of creating isolated power

sources using beads on surface traces. No power or

ground plane partitioning is implied or required.

By placing chassis ground on the top and bottom layers,

additional EMI shielding is created around the 125Mb/s sig-

nal traces that must be routed between the magnetics and

the RJ45-8 media connector. The example in Figure 24

assumes the use of Micro-Strip impedance control tech-

niques for trace routing.

Figure 23. Power and Ground Filtering for the DP83843

= FERRITE BEAD TDK # HF70ACB-321611T

ALL CAPS ARE 16V CERAMIC

DP83843

CD_GND0(#71),

TR_AVDD(#79)

TW_AGND(#64)

TW_AVDD(#68)

CD_VDD0(#72),

TR_AGND(#80)

VCC

GND

0.1UF

VCC

0.1UF

GND

VCC

0.1UF

0.001UF

0.1UF

0.0033UF

GND

ALTHOUGH THE FB’S TO GND REDUCE NOISE ON

THESE TWO CRITICAL PINS, THEY MAY INCREASE

EMI EMISSIONS. THEREFORE, DEPENDING ON

YOUR APPLICATION THEY MAY OR MAY NOT BE

A BENEFIT.

GND

IO_VSS1(#7),

VCC

GND

0.1UF

0.001UF

GND

VCC

0.0033UF

SUB_GND1(#70)

GND

10UF

CD_GND1(#75),

PCS_VSS(#11)

CD_VDD1(#76),

PCS_VDD(#10)

IO_VDD1(#6),

IO_VDD2(#16),

IO_VDD3(#26),

IO_VDD5(#36)

IO_VSS2(#17),

IO_VSS3(#27),

IO_VSS4(#32),

IO_VSS5(#37)

Ω AT 100MHZ

DP83843 Datasheet(PDF) 39 Page - National Semiconductor (TI)

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