DP83843 datasheet(18/87 Pages) NSC

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2.0 Functional Description (Continued)

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The 100BASE-TX MLT-3 signal sourced by the TPTD

+/−

common driver output pins is slow rate controlled. This

should be considered when selecting AC coupling magnet-

ics to ensure TP-PMD compliant transition times (3 ns < Tr

< 5ns).

The 100BASE-TX transmit TP-PMD function within the

DP83843 is capable of sourcing only MLT-3 encoded data.

Binary output from the TPTD

+/− outputs is not possible in

100 Mb/s mode.

2.2.4 TX_ER

Assertion of the TX_ER input while the TX_EN input is also

asserted will cause the DP83843 to substitute HALT code-

groups for the 5B data present at TXD[3:0]. However, the

SSD (/J/K/) and ESD (/T/R/) will not be substituted with

Halt code-groups. As a result, the assertion of TX_ER

while TX_EN is asserted will result in a frame properly

encapsulated with the /J/K/ and /T/R/ delimiters which con-

tains HALT code-groups in place of the data code-groups.

2.2.5 TXAR100

The transmit amplitude of the signal presented at the

TPTD

+/− output pins can be controlled by varying the value

of resistance between TXAR100 and system GND. This

TXAR100 resistor sets up a reference current that deter-

mines the ﬁnal output current at TPTD

+/−.

For 100

Ω Category-5 UTP cable implementations, the

TXAR100 resistor may be omitted as the DP83843 was

designed to source a nominal 2V pk-pk differential transmit

amplitude with this pin left ﬂoating. Setting the transmit

amplitude to 2V pk-pk differential (MLT-3) as measured

across the RJ45-8 transmit pins is critical for complying

with the IEEE/ANSI TP-PMD speciﬁcation of 2.0V pk-pk

differential

± 5%.

2.3 100BASE-TX RECEIVER

The 100BASE-TX receiver consists of several functional

blocks which convert the scrambled MLT-3 125 Mb/s serial

data stream to synchronous 4-bit nibble data that is pro-

vided to the MII. Because the 100BASE-TX TP-PMD is

integrated, the differential input pins, TPRD

+/−, can be

directly routed to the AC coupling magnetics.

See Figure 5 for a block diagram of the 100BASE-TX

receive function. This provides an overview of each func-

tional block within the 100BASE-TX receive section.

The Receive section consists of the following functional

blocks:

— Input and BLW Compensation

— Signal Detect

— Digital Adaptive Equalization

— MLT-3 to Binary Decoder

— Clock Recovery Module

— NRZI to NRZ Decoder

— Serial to Parallel

— DESCRAMBLER (bypass option)

— Code Group Alignment

— 4B/5B Decoder (bypass option)

— Link Integrity Monitor

— Bad SSD Detection

The bypass option for the functional blocks within the

100BASE-X receiver provides ﬂexibility for applications

such as 100 Mb/s repeaters where data conversion is not

always required.

2.3.1 Input and Base Line Wander Compensation

Unlike the DP83223V TWISTER™, the DP83843 requires

no external attenuation circuitry at its receive inputs,

TPRD

+/−. The DP83843 accepts TP-PMD compliant wave-

forms directly, requiring only a 100

Ω termination plus a

simple 1:1 transformer. The DP83843 also requires exter-

nal capacitance to VCC at the VCM_CAP pin (refer to Fig-

ure 23). This establishes a solid common mode voltage

that is needed since the TPRD pins are used in both 10

Mb/s and 100 Mb/s modes.

The DP83843 is completely ANSI TP-PMD compliant

because it compensates for baseline wander. The BLW

compensation block can successfully recover the TP-PMD

deﬁned “killer” pattern and pass it to the digital adaptive

equalization block.

Baseline wander can generally be deﬁned as the change in

the average DC content, over time, of an AC coupled digital

transmission over a given transmission medium. (i.e. cop-

per wire).

Baseline wander results from the interaction between the

low frequency components of a bit stream being transmit-

ted and the frequency response of the AC coupling compo-

nent(s) within the transmission system. If the low frequency

content of the digital bit stream goes below the low fre-

quency pole of the AC coupling transformers then the

droop characteristics of the transformers will dominate

resulting in potentially serious baseline wander.

It is interesting to note that the probability of a baseline wan-

der event serious enough to corrupt data is very low. In fact,

it is reasonable to virtually bound the occurrence of a base-

line wander event serious enough to cause bit errors to a

legal but premeditated, artificially constructed bit sequence

loaded into the original MAC frame. Several studies have

been conducted to evaluate the probability of various base-

line wander events for FDDI transmission over copper. Con-

tact the X3.263 ANSI group for further information.

2.3.2 Signal Detect

The signal detect function of the DP83843 is incorporated

to meet the speciﬁcations mandated by the ANSI FDDI TP-

PMD Standard as well as the IEEE 802.3 100BASE-TX

Standard for both voltage thresholds and timing parame-

ters.

Note that the reception of Normal 10BASE-T link pulses

and fast link pulses per IEEE 802.3u Auto-Negotiation by

the 100BASE-X receiver do not cause the DP83843 to

assert signal detect.

While signal detect is normally generated and processed

entirely within the DP83843, it can be observed directly on

the CRS pin (pin 22) while the DP83843 is conﬁgured for

Symbol mode. Refer to Section 3.4 for further detail regard-

ing Symbol mode operation.

2.3.3 Digital Adaptive Equalization

When transmitting data at high speeds over copper twisted

pair cable, frequency dependent attenuation becomes a

concern. In high speed twisted pair signalling, the fre-

quency content of the transmitted signal can vary greatly

during normal operation based primarily on the random-

ness of the scrambled data stream. This variation in signal

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