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DP83843 Datasheet(PDF) 17 Page - National Semiconductor (TI) |
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DP83843 Datasheet(HTML) 17 Page - National Semiconductor (TI) |
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17 / 87 page ![]() 2.0 Functional Description (Continued) 17 www.national.com Table 2. 4B5B Code-Group Encoding/Decoding Name PCS 5B Code-group MII 4B Nibble Code DATA CODES 0 11110 0000 1 01001 0001 2 10100 0010 3 10101 0011 4 01010 0100 5 01011 0101 6 01110 0110 7 01111 0111 8 10010 1000 9 10011 1001 A 10110 1010 B 10111 1011 C 11010 1100 D 11011 1101 E 11100 1110 F 11101 1111 IDLE AND CONTROL CODES H 00100 Halt code-group - Error code I 11111 Inter-Packet Idle - 0000 (Note 1) J 11000 First Start of Packet - 0101 (Note 1) K 10001 Second Start of Packet - 0101 (Note 1) T 01101 First End of Packet - 0000 (Note 1) R 00111 Second End of Packet - 0000 (Note 1) INVALID CODES V 00000 0110 or 0101 (Note 2) V 00001 0110 or 0101 (Note 2) V 00010 0110 or 0101 (Note 2) V 00011 0110 or 0101 (Note 2) V 00101 0110 or 0101 (Note 2) V 00110 0110 or 0101 (Note 2) V 01000 0110 or 0101 (Note 2) V 01100 0110 or 0101 (Note 2) V 10000 0110 or 0101 (Note 2) V 11001 0110 or 0101 (Note 2) Note 1: Control code-groups I, J, K, T and R in data fields will be mapped as invalid codes, together with RX_ER asserted. Note 2: Normally, invalid codes (V) are mapped to 6h on RXD[3:0] with RX_ER asserted. If the CODE_ERR bit in the PCS (bit 3, register address 16h) is set, the invalid codes are mapped to 5h on RXD[3:0] with RX_ER asserted. Refer to Section 4.14 for further detail. |
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