DP83843 datasheet(8/87 Pages) NSC

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1.0 Pin Descriptions (Continued)

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1.3 Clock Interface

1.4 Device Configuration Interface

Signal Name

Type

Pin #

Description

CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference input for

the DP83843 and must be connected to a 25 MHz 0.005% (50 ppm) clock source.

The DP83843 device supports either an external crystal resonator connected across

pins X1 and X2, or an external CMOS-level oscillator source connected to pin X1

only. For 100 Mb/s repeater applications, X1 should be tied to the common 25 MHz

transmit clock reference. Refer to section 4.4 for further detail relating to the clock

requirements of the DP83843. Refer to section 4.0 for clock source specifications.

CRYSTAL/OSCILLATOR OUTPUT PIN: This pin is used in conjunction with the X1

pin to connect to an external 25 MHz crystal resonator device. This pin must be left

unconnected if an external CMOS oscillator clock source is utilized. For more infor-

mation see the definition for pin X1. Refer to section 2.8 for further detail.

Signal Name

Type

Pin #

Description

AN0

(3-level)

AN0: This is a three level input pin (1, M, 0) that works in conjunction with the AN1

pin to control the forced or advertised operating mode of the DP83843 according to

the following table. The value on this pin is set by connecting the input pin to GND

(0), VCC (1), or leaving it unconnected (M.) The unconnected state, M, refers to the

mid-level (VCC/2) set by internal resistors. The value set at this input is latched into

the DP83843 at power-up/reset.

AN1

(3-level)

AN1: This is a three-level input pin (i.e., 1, M, 0) that works in conjunction with the

AN0 pin to control the forced or advertised operating mode of the DP83843 accord-

ing to the table given in the AN0 pin description above. The value on this pin is set

by connecting the input pin to GND (0), VCC (1), or leaving it unconnected (M.) The

value at this input is latched into the DP83843 at power-up, hardware or software

reset.

AN1

AN0

Forced Mode

10BASE-T, Half-Duplex without Auto-Negotiation

10BASE-T, Full Duplex without Auto-Negotiation

100BASE-X, Half-Duplex without Auto-Negotiation

100BASE-X, Full Duplex without Auto-Negotiation

AN1

AN0

Advertised Mode

All capable (i.e. Half-Duplex & Full Duplex for 10BASE-T and

100BASE-TX) advertised via Auto-Negotiation

10BASE-T, Half-Duplex & Full Duplex advertised via Auto-

Negotiation

100BASE-TX, Half-Duplex & Full Duplex advertised via

Auto-Negotiation

10BASE-T & 100BASE-TX, Half-Duplex advertised via Auto-

Negotiation

10 BASE-T, Half-Duplex advertised via Auto-Negotiation

DP83843 Datasheet(PDF) 8 Page - National Semiconductor (TI)

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