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DP83843 Datasheet(PDF) 9 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Part # DP83843
Description  PHYTER
PDF  87 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP83843 Datasheet(HTML) 9 Page - National Semiconductor (TI)

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1.0 Pin Descriptions (Continued)
9
www.national.com
REPEATER
(THIN)
I/O
63
REPEATER/NODE MODE: Selects 100 Mb/s Repeater mode when set high and
node mode when set low. When set in Repeater mode the DP83843 only supports
100 Mb/s data rates. In Repeater mode (or Node mode with Full Duplex config-
ured), the Carrier Sense (CRS) output from the DP83843 is asserted due to
receive activity only. In Half Duplex Node mode, CRS is asserted due to either
receive or transmit activity. During repeater mode the heartbeat function(SQE) is
forced off.
The Carrier Integrity Monitor (CIM) function is automatically enabled when this pin
is set high (repeater mode) and disabled when this pin is set low (node mode) in
order to facilitate 802.3u CIM requirements.
There is an internal pullup resistor for this pin which is active during the power-
up/reset period. If this pin is left floating externally, then the device will configure to
100 Mb/s Repeater mode as a result of power-up/reset. This pin must be externally
pulled low (typically 10 k
Ω) in order to configure the DP83843 for Node operation.
The value of this input is latched into the DP83843 at power-up, hardware or soft-
ware reset.
SYMBOL/
(CRS)
I/O, Z
22
SYMBOL MODE: This active low input allows 100 Mb/s transmit and receive data
streams to bypass all of the transmit and receive operations when set low. Note
that the PCS signals (CRS, RX_DV, RX_ER, and COL) have no meaning during
this mode. During Symbol operation, pins RX_ER/RXD[4] and TX_ER/TXD[4] are
used as the MSB of the 5 bit RX and TX data symbols.
There is an internal pullup resistor for this pin which is active during the power-
up/reset period. If this pin is left floating externally, then the device will configure to
normal mode as a result of power-up/reset. This pin must be externally pulled low
(typically 10 k
Ω) in order to configure the DP83843 for Symbol mode operation.
In Symbol mode this pin will indicate the signal detect status of the TP-PMD (active
high).
This mode has no effect on 10Mb/s operation. The value at this input is latched into
the DP83843 at power-up, hardware or software reset.
SERIAL10
I
69
10BASE-T SERIAL/NIBBLE SELECT: With this active low input selected, transmit
and receive data are exchanged serially at a 10 MHz clock rate on the least signifi-
cant bits of the nibble-wide MII data buses, pins TXD[0] and RXD[0] respectively.
This mode is intended for use with the DP83843 connected to a MAC using a 10
Mb/s serial interface. Serial operation is not supported in 100 Mb/s mode, therefore
this input is ignored during 100 Mb/s operation.
There is an internal pullup resistor for this pin which is active during the power-
up/reset period. If this pin is left floating externally, then the device will configure to
normal mode as a result of power-up/reset. This pin must be externally pulled low
(typically 10 k
Ω) in order to configure the DP83843 for Serial MII operation when
running at 10 Mb/s.
The value at this input is latched into the DP83843 at power-up, hardware or soft-
ware reset.
FXEN/
(COL)
I/O, Z
21
FIBER ENABLE: This active low input allows 100 Mb/s transmit and receive data
streams to bypass the scrambler and descrambler circuits when selected. All PCS
signaling remains active and unaffected during this mode. During this mode, the
internal 100 Mb/s transceiver is disabled, and NRZI data is transmitted and
received via the FXTD/AUITD
+/− and FXRD/AUIRD+/− pins.
There is an internal pullup resistor for this pin which is active during the power-
up/reset period. If this pin is left floating externally, then the device will configure to
normal mode as a result of power-up/reset. This pin must be externally pulled low
(typically 10 k
Ω) in order to configure the DP83843 for 100BASE-FX operation.
The value at this input is latched into the DP83843 at power-up, hardware or soft-
ware reset.
Signal Name
Type
Pin #
Description



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