DP83861 datasheet(5/88 Pages) NSC

5 / 88 page

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1.0 Pin Descriptions

The DP83861 pins are classified into the following interface

categories (each is described in the sections that follow):

— MAC Interface

— TP Interface

— JTAG Interface

—E2PROM Interface

— Clock Interface

— LED Interface

— Device Configuration / Strapping Options

—Reset

— Power and Ground Pins

— Special Connect Pins

Note: Strapping pin option

(BOLD) (e.g. AN_EN)

Type: I

Inputs

Type: O

Output

Type: O_Z

Tristate Output

Type: I/O_Z

Tristate Input_Output

Type: S

Strapping Pin

Type: PU

Pull-up

Type: PD

Pull-down

1.1 MAC Interface

Signal Name

Type

Pin #

Description

MDC

151

MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO

management data input/output serial interface which may be asyn-

chronous to transmit and receive clocks. The maximum clock rate is

2.5 MHz with no minimum clock rate.

MDIO

I/O

150

MANAGEMENT DATA I/O: Bi-directional management instruc-

tion/data signal that may be sourced by the station management en-

tity or the PHY. This pin requires a 1.5 k

Ω pullup resistor.

CRS

111

CARRIER SENSE: Asserted high to indicate the presence of carrier

due to receive or transmit activity in Half Duplex mode. This signal is

not defined (LOW) for 1000BASE-T Full Duplex mode. For

1000BASE-T, 100BASE-TX and 10BASE-T Full Duplex operation

CRS is asserted only for receive activity.

COL

110

COLLISION DETECT: Asserted high to indicate detection of a colli-

sion condition (assertion of CRS due to simultaneous transmit and re-

ceive activity) in Half Duplex modes. This signal is not synchronous

to either MII clock (GTX_CLK, TX_CLK or RX_CLK). This signal is not

defined (LOW) for Full Duplex modes.

TX_CLK

130

TRANSMIT CLOCK (10 Mb/s and 100 Mb/s): Continuous clock sig-

nal generated from REF_CLK and driven by the PHY during 10Mb/s

and 100 Mb/s operation. It is used on the MII to clock all MII Transmit

(data, error) signals into the PHY.

The Transmit Clock frequency is constant and the frequency is

2.5 MHz for 10Mb/s mode and 25 MHz for 100Mb/s mode.

TX_CLK should not be confused with the TX_TCLK signal.

TXD0

TXD1

TXD2

TXD3

TXD4

TXD5

TXD6

TXD7

146

145

144

141

140

139

138

135

TRANSMIT DATA: These signals carry 4B data nibbles (TXD[3:0])

during 10 Mb/s and 100 Mb/s MII mode and 8-bit data (TXD[7:0]) in

1000 Mb/s GMII mode. They are synchronous to the Transmit Clocks

(TX_CLK, GTX_CLK. Transmit data is input enabled by TX_EN for all

modes all sourced by the controller.

TX_EN

134

TRANSMIT ENABLE: Active high input driven by the MAC request-

ing transmission of the data present on the TXD lines (nibble data for

10 Mb/s and 100 Mb/s mode and 8-bit data for 1000 Mb/s GMII

mode.)

GTX_CLK

147

GMII-TRANSMIT CLOCK: This continuous clock signal is sourced

from the upper level MAC to the PHY. Nominal frequency of 125 MHz,

derived in the MAC from its 125 MHz reference clock.

DP83861 Datasheet(PDF) 5 Page - National Semiconductor (TI)

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