DP83861 datasheet(17/88 Pages) NSC

17 / 88 page

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3.0 Design and Layout Guide

This guide will provide information to assist in the design

and layout of the DP83861 Gigabit Ethernet Transceiver.

This guide will cover the following areas:

— Power Supply Filtering

— Twisted Pair Interface

— MAC Interface

—Clocks

— LED/Strapping Configuration

— Unused Pins/ Reserved Pins

— Hardware Reset

— Temperature Considerations

— List of Pins and Pin Connection Guide

3.1 Power Supply Filtering

It is recommended that the PCB have at least one solid

ground plane, one solid 3.3 V plane, and one solid 1.8 V

plane, with no breaks in any of these planes. The inter-

plane capacitance between the supply and ground planes

should be maximized by minimizing the distance between

these planes. Filling unused signal planes with copper and

connecting them to the proper power plane will also

increase the interplane capacitance. The inter-plane

capacitance acts like a short at high frequencies to reduce

supply plane impedance. Not all designs will be able to

incorporate the recommended suggestions because of

board cost constraints. Working designs have been done

using only 4 layers. National has a reference design built

using the EN Gig PHYTER and our GigMAC. This refer-

ence design is a PCI NIC card, using only 4 layers and

having component placement on only one side of the board

to reduce cost. The schematic, layout and gerber files for

this reference design are available upon request.

The 3.3 V & the 1.8 V supply pins come in pairs with their

corresponding ground pins (i.e. a 3.3 V supply-ground pair

is formed by pin 2 [RA_AVDD] and pin 3 [RA_AGND]).

These paired pins are physically adjacent to each other.

The matching pins should be bypassed with low imped-

ance surface mount capacitors of value 0.1

µF connected

directly into the power planes with vias as close as possible

to the pins. This will reduce the inductance in series with

the bypass capacitor. Any increase in inductance will lower

the capacitor’s self resonant frequency which will degrade

the high frequency performance of the capacitor. It’s also

recommended that 0.01

µF capacitors are connected in

parallel with the 0.1

µF capacitors, or at least "dispersed",

replacing some of the 0.1

µF capacitors. The lower value

capacitance will increase the frequency range of effective-

ness of the bypassing scheme. This is due to the unavoid-

able inductance of the leads and connections on the board,

which cause resonance at low frequencies for large value

capacitors.

The Analog PGM supply requires special filtering to attenu-

ate high frequencies. High frequencies will increase the jit-

ter of the PGM. We recommend a low pass filter formed by

a 18-22

Ω resistor and two capacitors in parallel. One of

the capacitors should be 22

µF and the other 0.01 µF. (This

will implement a single pole low pass filter with 3 dB freq.

around 360 - 400 Hz.). The maximum current on this sup-

ply is 5 mA.

Figure 1. Power Supply Filtering

D P 83 86 1

Ω − 22 Ω

VDD = 3 .3 V

0.01

µF

Ty pic a l su pply by pas sing

Low pas s filter fo r

µF

PG M _ A VDD

PG M _ AG N D

0.1

µF

IO _ VDD

IO _ G N D

(N ear p ins of th e devic e)

BG _ A VDD

AG N D

BG _ R EF

9 .31 k

Ω

0.01

µF

P G M _ AV D D only

0.01

µF

CO RE _ VDD

0.1

µF

0.01

µF

VDD = 1.8 V

CO RE _ VSS

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