DP83861 datasheet(7/88 Pages) NSC

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1.3 JTAG Interface

RXDA+

RXDA-

RXDB-

RXDB+

RXDC+

RXDC-

RXDD-

RXDD+

RECEIVE DATA: Differential receive signals.

NOTE: During 10/100 Mb/s operation only RXDB+ and RXDB- or

RXDA+ and RXDA- are active (See DP83861 Datasheet for automat-

ic crossover configuration.)

Signal Name

Type

PIn #

Description

Signal Name

Type

PIn #

Description

TRST

156

TEST RESET: IEEE 1149.1 Test Reset pin, active low reset provides

for asynchronous reset of the Tap Controller. This reset has no effect

on the device registers.

This pin should be tied low during regular chip operation.

TDI

157

TEST DATA INPUT: IEEE 1149.1 Test Data Input pin, test data is

scanned into the device via TDI.

This pin should be tied low during regular chip operation.

TDO

158

TEST DATA OUTPUT: IEEE 1149.1 Test Data Output pin, the most

recent test results are scanned out of the device via TDO.

This pin can be left floating if not used.

TMS

159

TEST MODE SELECT: IEEE 1149.1 Test Mode Select pin, the TMS

pin sequences the Tap Controller (16-state FSM) to select the desired

test instruction.

This pin should be tied low during regular chip operation.

TCK

163

TEST CLK: IEEE 1149.1 Test Clock input, primary clock source for

all test logic input and output controlled by the testing entity.

This pin should be tied low during regular chip operation.

DP83861 Datasheet(PDF) 7 Page - National Semiconductor (TI)

DP83861 Datasheet(HTML) 7 Page - National Semiconductor (TI)

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