DP83861 datasheet(6/88 Pages) NSC

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1.2 TP Interface

TX_ER

133

TRANSMIT ERROR: Active high input during 100 Mb/s nibble mode

or 1000 Mb/s GMII mode. This forces the PHY to transmit invalid sym-

bols. The TX_ER signal must be synchronous to the Transmit Clocks

(TX_CLK and GTX_CLK).

In 4B nibble mode, assertion of Transmit Error by the controller caus-

es the PHY to issue invalid symbols followed by Halt (H) symbols until

deassertion occurs.

In 1000 Mb/s GMII mode, assertion causes the PHY to emit one or

more code-groups that are not valid data or delimiter set in the trans-

mitted frame.

RX_CLK

126

RECEIVE CLOCK: Provides the recovered receive clocks for differ-

ent modes of operation:

2.5 MHz nibble clock in 10 Mb/s MII mode.

25 MHz nibble clock in 100 Mb/s MII mode.

125 MHz byte clock in 1000 Mb/s GMII mode.

RXD0

RXD1

RXD2

RXD3

RXD4

RXD5

RXD6

RXD7

125

124

121

120

119

118

115

114

RECEIVE DATA: These signals carry 4-bit data nibbles (RXD[3:0])

during 10Mb/s and 100 Mb/s MII mode and 8-bit data (RXD[7:0]) in

1000 Mb/s GMII mode. They are synchronous to the Receive Clock

(RX_CLK). Receive data is driven by the PHY to the controller, and is

strobed by Receive Data Valid (RX_DV) which is also sourced by the

PHY.

RX_ER

112

RECEIVE ERROR: In 100 Mb/s MII mode and 1000 Mb/s GMII mode

this active high output indicates that the PHY has detected a Receive

Error. The RX_ER signal must be synchronous with the Receive

Clock (RX_CLK).

RX_DV

113

RECEIVE DATA VALID: Asserted high to indicate that valid data is

present on the corresponding RXD[3:0] for 10 Mb/s or 100 Mb/s MII

mode and RXD[7:0] in 1000 Mb/s GMII mode.

Signal Name

Type

Pin #

Description

Signal Name

Type

PIn #

Description

TXDA+

TXDA-

TXDB-

TXDB+

TXDC+

TXDC-

TXDD-

TXDD+

TRANSMIT DATA: The TP Interface connects the DP83861 to the

CAT-5 cable through a single common magnetics transformer. The

Transmit (TXD) and Receive (RXD) Twisted Pair pins carry bit-serial

data at 125 MHz baud rate. These differential outputs are config-

urable to either 100 BASE-T, 100BASE-TX or 1000BASE-T signal-

ling:

10BASE-T: Transmission of MANCHESTER encoded signals. The

10BASE-T signal does not meet IEEE transmit output voltages. See

Section 7.1.

100BASE-TX: Transmission of 3-level MLT-3 data.

1000BASE-T: Transmission of 17-level PAM-5 with PR-shaping data.

The DP83861 will automatically configure the common driver outputs

for the proper signal type as a result of either forced configuration or

Auto-Negotiation.

NOTE: During 10/100 Mb/s operation only TXDA+ and TXDA- or

TXDB+ and TXDB- are active. (See DP83861 Datasheet for automat-

ic crossover configuration.)

DP83861 Datasheet(PDF) 6 Page - National Semiconductor (TI)

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