DP83861 datasheet(18/88 Pages) NSC

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A 10

µF capacitor should also be placed close to the

DP83861 (possibly on the bottom side of the PCB) bypass-

ing the VCC and ground planes.

There has been considerable discussion in the literature

about the use of ferrite beads to isolate power plane noise

from certain noisy VCC pins and preventing this noise from

coupling into sensitive analog VCC pins. This is typically

achieved by using ferrite beads (inductors) between noisy

VCC and quiet VCC line. An inductor in conjunction with

the bypass capacitor at the VCC pins will form a low pass

filter which will prevent the high frequency noise from cou-

pling into the quite VCC. However, using this scheme can

give mixed results. There is considerable debate about

whether this approach is necessary or even useful. In most

of our boards we put in a stuffing option for inductors (zero

Ohm resistors). In general we have not found any improve-

ments with the use of ferrite beads, however noise consid-

erations are very dependent on PCB’s specific layout,

function and power supplies. The board designer should

evaluate whether they will benefit from ferrite beads in their

particular board.

The pin check list on Table 14 show the suggested connec-

tions of these capacitors for every supply, ground and sub-

strate pin.

3.2 Twisted Pair Interface

The Twisted Pair Interface consists of four differential

transmit pairs (Channels A, B, C, and D) and four differen-

tial receive pairs (Channels A, B, C, and D). Each transmit

pair is connected to its’ corresponding receive pair through

Ω and 150 Ω resistors respectively (The two 47 Ω resis-

tors in combination with the source impedance of the trans-

mitter will form a 100

Ω differential input impedance as

seen from the line. This is required to minimize reflec-

tions.). Figure 2 shows a typical connection for Channel A.

Channels B, C, and D are identical. The combined transmit

and receive trace then goes directly to 1:1 magnetics. We

currently recommend using the Pulse H-5007 or Pulse H-

5008. Both magnetics are pin for pin compatible, but with

different package orientations. The H-5007/8 has an isola-

tion transformer followed by a common mode choke to

reduce EMI. There is an additional auto-transformer which

is center tapped. These 2 transformers as well as other

suppliers’ transformers from Halo, Belfuse, Transpower,

Midcom, etc. should be evaluated for best performance for

each design. See Table 9 and Table 10.

— Place the 47

Ω 1% transmit resistors as close as possi-

ble to the TXDA+/-, TXDB+/-, TXDC+/-, and TXD+/- pins

— Place the 150

Ω 1% receive resistors close as possible

to the RXDA+/-, RXDB+/-, RXDC+/-, and RXDD+/- pins.

— All traces to and from the twisted pair interface should

have a controlled impedance of 50

Ω to the ground

plane. This is a strict requirement. They should be as

close in length to each other as possible to prevent mis-

matches in delay which will increase common mode

noise.

Ideally there should be no crossovers or vias on the signal

paths of these traces.

3.3 MAC Interface

The DP83861 can be configured in one of two different

modes:

— GMII (Gigabit Media Independent Interface) MODE: This

interfaces is used to support 802.3z compliant 1000

Mb/s MACs.

— MII (Media Independent Interface) MODE: This interface

is used to support 10/100 Mb/s MACs.

Only one mode can be supported at a time, since the GMII

and MII share some pins in common.

These outputs are capable of driving 35 pF under worst

case conditions. These outputs were not designed to drive

multiple loads, connectors, backplanes, or cables. It is rec-

ommended that the outputs be series terminated through a

resistor as close to the output pins as possible. The pur-

pose of the series termination is to reduce reflections on

the line. The value of the series termination and length of

trace the output can drive will depend on the driver output

impedance, the characteristic impedance of the PCB trace

(we recommend 50

Ω), the distributed trace capacitance

(capacitance/inch), and the load capacitance (MAC input).

For short traces, less than 0.5 inches, the series resistors

may not be required, thus reducing component count.

However, each specific board design should be evaluated

for reflections and signal integrity to determine the need for

the series terminations. As a general rule of thumb, if the

trace length is less than 1/6 of the equivalent length of the

100 pF

Ω

Only the connections for one of the twisted pair channels is shown. Connections for channels B, C, D are similar.

Figure 2. Twisted Pair / Magnetics Interface (Channel A Only)

0.1

µF

TD4-

TCT4

TD4+

MX4+

MX4-

MCT4

TXDA+

TXDA-

RXDA+

RXDA-

A+

A-

B+

B-

C+

C-

D+

D-

Chassis Ground

3 kV

D P83861

PU L SE H -5 0 0 7

RJ -4 5

Ω

150

Ω

150

Ω

Chassis Ground

DP83861 Datasheet(PDF) 18 Page - National Semiconductor (TI)

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